research-article

Reducing NBTI-induced processor wearout by exploiting the timing slack of instructions

Authors:

Farshad Firouzi,

Mehdi TahooriAuthors Info & Claims

CODES+ISSS '12: Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Pages 443 - 452

https://doi.org/10.1145/2380445.2380514

Published: 07 October 2012 Publication History

Abstract

Transistor aging due to Negative Bias Temperature Instability (NBTI) is a major reliability challenge for embedded microprocessors at nanoscale. It leads to increasing path delays and eventually more failures during runtime. In this paper, we propose a novel microarchitectural approach combining aging-aware instruction scheduling with specialized functional units to alleviate the impact of NBTI-induced wearout. To achieve this, the instructions are classified depending on their worst-case delay into critical (i.e. the instructions whose delay is close to the cycle boundary) and non-critical instructions (i.e. those instruction with larger timing slack). Each of these classes uses its own (specialized) functional unit(s). By that means it is possible to increase the idle ratio of the units executing the critical instructions, which can be used to extend lifetime by up to 2.3x in average compared to the usually used balanced scheduling policy.

References

[1]

miniMIPS. Opencores: http://opencores.org/project,minimips. {Online;accessed July 2012}.

[2]

OpenRisc 1200. Opencores: http://opencores.org/project,or1200_hp. {Online;accessed July 2012}.

[3]

J. Abella, X. Vera, and A. Gonzalez. Penelope: The NBTI-Aware Processor. In Proc. of the Int'l Symp. on Microarchitecture, pp. 85--96, Dec. 2007.

Digital Library

[4]

ARM Limited. Cortex-A8 Technical Reference Manual, 2010.

[5]

M. Basoglu, M. Orshansky, and M. Erez. NBTI-Aware DVFS: A New Approach to Saving Energy and Increasing Processor Lifetime. In Proc. of the Int'l Symp. on Low Power Electronics and Design, pp. 253--258, Aug. 2010.

Digital Library

[6]

K. Bernstein, D. J. Frank, A. E. Gattiker, W. Haensch, B. L. Ji, S. R. Nassif, E. J. Nowak, D. J. Pearson, and N. J. Rohrer. High-performance CMOS variability in the 65-nm regime and beyond. IBM Journal of Research and Development - Advanced silicon technology, 50, pp. 433--449, July 2006.

Digital Library

[7]

S. Bhardwaj, W. Wang, R. Vattikonda, Y. Cao, and S. Vrudhula. Predictive modeling of the NBTI effect for reliable design. In Proc. Custom Integrated Circuits Conf., pp. 189--192, 2006.

[8]

D. Bild, G. Bok, and R. Dick. Minimization of NBTI performance degradation using internal node control. In Proc. of the Conf. on Design, Automation and Test in Europe, pp. 148--153, Mar. 2009.

Digital Library

[9]

N. L. Binkert, R. G. Dreslinski, L. R. Hsu, K. T. Lim, A. G. Saidi, and S. K. Reinhardt. The M5 Simulator: Modeling Networked Systems. IEEE Micro, 26(4), pp. 52--60, July 2006.

Digital Library

[10]

S. Borkar. Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation. IEEE Micro, 25(6), pp. 10--16, Nov. 2005.

Digital Library

[11]

K. A. Bowman, B. L. Austin, J. C. Eble, X. Tang, and J. D. Meindl. A Physical Alpha-Power Law MOSFET Model. In Proc. of the Int'l Symp. on Low Power Electronics and Design, pp. 218--222, Aug. 1999.

Digital Library

[12]

A. Calimera, E. Macii, and M. Poncino. NBTI-Aware Power Gating for Concurrent Leakage and Aging Optimization. In Proc. of the Int'l Symp. on Low Power Electronics and Design, pp. 127--132, Aug. 2009.

Digital Library

[13]

T. Chan, J. Sartori, P. Gupta, and R. Kumar. On the Efficacy of NBTI Mitigation Techniques. In Proc. of the Conf. on Design, Automation and Test in Europe, pp. 1--6, Mar. 2011.

[14]

N. Choudhary, S. Wadhavkar, T. Shah, H. Mayukh, J. Gandhi, B. Dwiel, S. Navada, H. Najaf-abadi, and E. Rotenberg. FabScalar: Automating Superscalar Core Design. IEEE Micro, 32(3), pp. 48--59, May 2012.

Digital Library

[15]

F. Firouzi, S. Kiamehr, and M. B. Tahoori. A Linear Programming Approach for Minimum NBTI Vector Selection. In Proc. of the Great Lakes Symp. on VLSI, pp. 253--258, May 2011.

Digital Library

[16]

F. Firouzi, S. Kiamehr, and M. B. Tahoori. NBTI Mitigation by NOP Assignment and Insertion. In Proc. of the Conf. on Design, Automation and Test in Europe, pp. 218--223, Mar. 2012.

Digital Library

[17]

J. L. Hennessy, D. A. Patterson, and D. Goldberg. Computer Architecture: A Quantitative Approach. Morgan Kaufmann, 2003.

Digital Library

[18]

W. Huang, S. Ghosh, S. Velusamy, K. Sankaranarayanan, K. Skadron, and M. R. Stan. HotSpot: A Compact Thermal Modeling Methodology for Early-Stage VLSI Design. Trans. on Very Large Scale Integration Systems, 14(5), pp. 501--513, May 2006.

Digital Library

[19]

R. Islam, A. Sabbavarapu, and R. Patel. Power Reduction Schemes in Next Generation Intel ATOM Processor Based SoC for Handheld Applications. In Symp. on VLSI Circuits, pp. 173--174, June 2010.

[20]

S. Kim, S. V. Kosonocky, and D. R. Knebel. Understanding and Minimizing Ground Bounce During Mode Transition of Power Gating Structure. In Proc. of the Int'l Symp. on Low Power Electronics and Design, pp. 22--25, Aug. 2003.

Digital Library

[21]

R. Kumar and G. Hinton. A Family of 45nm IA Processors. In Proc. of the IEEE Int'l Solid-State Circuits Conf., pp. 58--59, Feb. 2009.

[22]

S. Li, J. H. Ahn, R. D. Strong, J. B. Brockman, D. M. Tullsen, and N. P. Jouppi. McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures. In Proc. of the Int'l Symp. on Microarchitecture, pp. 469--480, Dec. 2009.

Digital Library

[23]

S. Naidu and E. Jacobs. Minimizing Stand-by Leakage Power in Static CMOS Circuits. In Proc. of the Conf. on Design, Automation and Test in Europe, pp. 370--376, Mar. 2001.

Digital Library

[24]

V. Narayanan and Y. Xie. Reliability Concerns in Embedded System Designs. Computer, 39(1), pp. 118--120, Jan. 2006.

Digital Library

[25]

F. Oboril and M. B. Tahoori. ExtraTime: Modeling and Analysis of Wearout due to Transistor Aging at Microarchitecture-Level. In Proc. of the Int'l Conf. on Dependable Systems and Networks, June 2012.

Digital Library

[26]

F. Oboril and M. B. Tahoori. Reducing Wearout in Embedded Processors using Proactive Fine-Grained Dynamic Runtime Adaptation. In Proc. of the European Test Symp., pp. 68--73, May 2012.

[27]

S. Pae, M. Agostinelli, M. Brazier, R. Chau, G. Dewey, T. Ghani, M. Hattendorf, J. Hicks, J. Kavalieros, K. Kuhn, M. Kuhn, J. Maiz, M. Metz, K. Mistry, C. Prasad, S. Ramey, A. Roskowski, J. Sandford, C. Thomas, J. Thomas, C. Wiegand, and J. Wiedemer. BTI Reliability of 45 nm High-K +Metal-Gate Process Technology. In Int'l Reliability Physics Symp., pp. 352--357, May 2008.

[28]

T. Siddiqua and S. Gurumurthi. A Multi-Level Approach to Reduce the Impact of NBTI on Processor Functional Units. In Proc. of the Great Lakes Symp. on VLSI, pp. 67--72, May 2010.

Digital Library

[29]

A. Tiwari and J. Torrellas. Facelift: Hiding and slowing down aging in multicores. In Proc. of the Int'l Symp. on Microarchitecture, pp. 129--140, Nov. 2008.

Digital Library

[30]

K. Usami, T. Shirai, T. Hashida, H. Masuda, S. Takeda, M. Nakata, N. Seki, H. Amano, M. Namiki, M. Imai, M. Kondo, and H. Nakamura. Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. In Int'l Conf. on VLSI Design, pp. 381--386, Jan. 2009.

Digital Library

[31]

N. J. Wang, J. Quek, T. M. Rafacz, and S. J. patel. Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline. In Proc. of the Int'l Conf. on Dependable Systems and Networks, pp. 61--71, June 2004.

Digital Library

[32]

W. Wang, S. Yang, S. Bhardwaj, S. Vrudhula, F. Liu, and Y. Cao. The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis. IEEE Trans. on Very Large Scale Integration Systems, 18(2), pp. 173--183, Feb. 2010.

Digital Library

[33]

Y. Wang, X. Chen, W. Wang, V. Balakrishnan, Y. Cao, Y. Xie, and H. Yang. On the efficiancy of Input Vector Control to mitigate NBTI effects and leakage power. In Proc. of the Int'l Symp. on Quality of Electronic Design, pp. 19--26, Mar. 2009.

Digital Library

[34]

Y. Wang, X. Chen, W. Wang, Y. Cao, Y. Xie, and H. Yang. Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques. IEEE Trans. on Very Large Scale Integration Systems, (99), pp. 1--14, 2011.

Digital Library

[35]

K. Wu and D. Marculescu. Joint Logic Restructuring and Pin Reordering against NBTI-induced Performance Degradation. In Proc. of the Conf. on Design, Automation and Test in Europe, pp. 75--80, Mar. 2009.

Digital Library

[36]

L. Yuan and G. Qu. Simultaneous Input Vector Selection and Dual Threshold Voltage Assignment for Static Leakage Minimization. In Proc. of the Int'l Conf. on Computer-Aided Design, pp. 548--551, 2007.

Digital Library

Cited By

Tahoori MGolanbari M(2020)Cross-Layer Reliability, Energy Efficiency, and Performance Optimization of Near-Threshold Data PathsJournal of Low Power Electronics and Applications10.3390/jlpea1004004210:4(42)Online publication date: 3-Dec-2020
https://doi.org/10.3390/jlpea10040042
Moghaddasi ISalehi Nasab MKargahi M(2020)Aging-Aware Instruction-Level Statistical Dynamic Timing Analysis for Embedded ProcessorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.294775728:2(433-442)Online publication date: Feb-2020
https://doi.org/10.1109/TVLSI.2019.2947757
Moghaddasi IFouman ASalehi MKargahi M(2019)Instruction-Level NBTI Stress Estimation and Its Application in Runtime Aging Prediction for Embedded ProcessorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.284662938:8(1427-1437)Online publication date: Aug-2019
https://doi.org/10.1109/TCAD.2018.2846629
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Index Terms

Reducing NBTI-induced processor wearout by exploiting the timing slack of instructions
1. Hardware
  1. Hardware test
  2. Robustness

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cover image ACM Conferences

CODES+ISSS '12: Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

October 2012

596 pages

ISBN:9781450314268

DOI:10.1145/2380445

General Chairs:
Ahmed Jerraya
CEA
,
Luca Carloni
Columbia University
,
Program Chairs:
Naehyuck Chang
Seoul National University, Korea
,
Franco Fummi
University of Verona, Italy

Copyright © 2012 ACM.

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Published: 07 October 2012

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ESWEEK'12: Eighth Embedded System Week

October 7 - 12, 2012

Tampere, Finland

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CODES+ISSS '12 Paper Acceptance Rate 48 of 163 submissions, 29%;

Overall Acceptance Rate 280 of 864 submissions, 32%

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Cited By

Tahoori MGolanbari M(2020)Cross-Layer Reliability, Energy Efficiency, and Performance Optimization of Near-Threshold Data PathsJournal of Low Power Electronics and Applications10.3390/jlpea1004004210:4(42)Online publication date: 3-Dec-2020
https://doi.org/10.3390/jlpea10040042
Moghaddasi ISalehi Nasab MKargahi M(2020)Aging-Aware Instruction-Level Statistical Dynamic Timing Analysis for Embedded ProcessorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.294775728:2(433-442)Online publication date: Feb-2020
https://doi.org/10.1109/TVLSI.2019.2947757
Moghaddasi IFouman ASalehi MKargahi M(2019)Instruction-Level NBTI Stress Estimation and Its Application in Runtime Aging Prediction for Embedded ProcessorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.284662938:8(1427-1437)Online publication date: Aug-2019
https://doi.org/10.1109/TCAD.2018.2846629
Nakhaee FKamal MAfzali-Kusha APedram MFakhraie SDorosti H(2018)Lifetime improvement by exploiting aggressive voltage scaling during runtime of error-resilient applicationsIntegration, the VLSI Journal10.1016/j.vlsi.2017.10.01361:C(29-38)Online publication date: 1-Mar-2018
https://dl.acm.org/doi/10.1016/j.vlsi.2017.10.013
Reddy PHadjitheophanous SSoteriou VGratz PMichael M(2017)Minimal exercise vector generation for reliability improvement2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)10.1109/IOLTS.2017.8046205(113-119)Online publication date: Jul-2017
https://doi.org/10.1109/IOLTS.2017.8046205
Das AKumar AVeeravalli BCatthoor FDas AKumar AVeeravalli BCatthoor F(2017)IntroductionReliable and Energy Efficient Streaming Multiprocessor Systems10.1007/978-3-319-69374-3_1(1-21)Online publication date: 4-Nov-2017
https://doi.org/10.1007/978-3-319-69374-3_1
Golanbari MGebregiorgis AOboril FKiamehr STahoori M(2016)A cross-layer approach for resiliency and energy efficiency in Near Threshold Computing2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1145/2966986.2980081(1-8)Online publication date: 7-Nov-2016
https://dl.acm.org/doi/10.1145/2966986.2980081
Sengupta DMishra VSapatnekar S(2016)Invited - Optimizing device reliability effects at the intersection of physics, circuits, and architectureProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2905016(1-6)Online publication date: 5-Jun-2016
https://dl.acm.org/doi/10.1145/2897937.2905016
Kashefi EZarandi HGordon-Ross A(2016)Postponing wearout failures in chip multiprocessors using thermal management and thread migration2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)10.1109/ReCoSoC.2016.7533906(1-7)Online publication date: Jun-2016
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Karimi NKanuparthi AWang XSinanoglu OKarri R(2015)MAGICACM Transactions on Architecture and Code Optimization10.1145/272471812:1(1-25)Online publication date: 2-Apr-2015
https://dl.acm.org/doi/10.1145/2724718
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