This paper presents a novel read-bitline amplitude limiting (RBAL) scheme which suppresses dynamic energy dissipation caused by random variation. In addition, a discharge acceleration (DA) circuit is proposed to decrease delay overhead of RBAL. The proposed scheme improves the active energy dissipation in a read cycle by 22% at the center-center (CC) corner and 25°C. The maximum delay overhead is 32% at the fast-slow (FS) corner and -40°C. The circuits have been implemented using the 40-nm bulk CMOS process. The implemented 256-Kb 8T SRAM works fine with energy dissipation of sub-10 pJ / access from 0.5-0.7 V.

References

[1]

A. J. Bhavnagarwala, X. Tang, and D. Meindl, "The Impact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability," Journal of Solid-State Circuits, Vol. 36, No. 4, 658--665, 2001.

Crossref

Google Scholar

[2]

R. Heald and P. Wang, "Variability in Sub-100nm SRAM Designs," Proc. of International Conference on Computer Aided Design, pp. 347--352, 2004.

Digital Library

Google Scholar

[3]

Y. Morita, K. Nose, K. Noguchi, S. Takami, K. Goto, Y. Aimoto, A. Kimura and M. Mizuno, "Small-defect detection in sub-100nm SRAM cells using a WL-pulse timing-margin measurement scheme," Digest of Technical Papers 2010 Symposium on VLSI Circuits, pp. 37--38, Jun. 2010.

Google Scholar

[4]

H. Pilo, J. Barwin, G. Braceras, C. Browning, S. Burns, J. Gabric, S. Lamphier, and M. Miller, "An SRAM Design in 65 nm and 45 nm Technology Nodes Featuring Read and Write-Assist Circuits to Expand Operating Voltage," IEEE Symposium on VLSI Circuits, pp. 15--16, June 2006.

Google Scholar

[5]

K. Takeda, T. Saito, S. Asayama, Y. Aimoto, H. Kobatake, S. Ito, T. Takahashi, K. Takeuchi, M. Nomura and Y. Hayashi, "Multi-step Word-line Control Technology in Hierarchical Cell Architecture for Scaled-down High-density SRAMs," Digest of Technical Papers 2010 Symposium on VLSI Circuits, pp. 101--102, Jun. 2010.

Google Scholar

[6]

Y. Fujimura, O. Hirabayashi, T. Sasaki, A. Suzuki, A. Kawasumi, Y. Takeyama, K. Kushida, G. Fukano, A. Katayama, Y. Niki, T. Yabe, "A Configurable SRAM with Constant-Negative-Level Write Buffer for Low-Voltage Operation with 0.149μ2 Cell in 32nm High-κ Metal-Gate CMOS," IEEE International Solid-State Circuits Conference, pp. 348--349, 2010.

Google Scholar

[7]

H. Nho, P. Kolar, F. Hamzaoglu, Y. Wang, E. Karl, Y. G. Ng, U. Bhattacharya and K. Zhang, "A 32nm High-κ Metal Gate SRAM with Adaptive Dynamic Stability Enhancement for Low-Voltage Operation," IEEE International Solid-State Circuits Conference, pp. 346--347, 2010.

Google Scholar

[8]

Y. Morita, H. Fujiwara, H. Noguchi, Y. Iguchi, K. Nii, H. Kawaguchi, and M. Yoshimoto, "An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment," IEEE Symposium on VLSI Circuits Digest of Technical Papers, pp. 256--257, Jun. 2007.

Google Scholar

[9]

Y. Pu, X. Zhang, J. Huang, A. Muramatsu, M. Nomura, K. Hirairi, H. Takata, T. Sakurabayashi, S. Miyano, M. Takamiya, and T. Sakurai, "Misleading Energy and Performance Claims in Sub/Near Threshold Digital Systems," Proc. of International Conference on Computer Aided Design, pp. 625--631, 2010.

Digital Library

Google Scholar

[10]

A. Kawasumi, T. Suzuki, S. Moriwaki and S. Miyano, "Energy Efficiency Degradation Caused by Random Variation in Low-Voltage SRAM and 26% Improvement by Bitline Amplitude Limiting (BAL) Scheme," IEEE Asian Solid-State Circuits Conference, pp. 165--168, Sep. 2011.

Google Scholar

[11]

S. Yoshimoto, M. Terada, S. Okumura, T. Suzuki, S. Miyano, H. Kawaguchi and M. Yoshimoto, "A 40-nm 0.5-V 20.1-uW/MHz 8T SRAM with Low-Energy Disturb Mitigation Scheme," Digest of Technical Papers 2011 Symposium on VLSI Circuits, pp. 72--73, Jun. 2011.

Google Scholar

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Li HPao CChen BTsai C(2013)AOT-controlled dual-mode AVP buck regulator with AEAF mechanismProceedings of the IEEE 2013 Custom Integrated Circuits Conference10.1109/CICC.2013.6658538(1-4)Online publication date: Sep-2013
https://doi.org/10.1109/CICC.2013.6658538
Yoshimoto SMiyano STakamiya MShinohara HKawaguchi HYoshimoto M(2013)A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structureProceedings of the IEEE 2013 Custom Integrated Circuits Conference10.1109/CICC.2013.6658537(1-4)Online publication date: Sep-2013
https://doi.org/10.1109/CICC.2013.6658537

Index Terms

A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Static memory

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ISLPED '12: Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design

July 2012

438 pages

ISBN:9781450312493

DOI:10.1145/2333660

General Chairs:
Naresh Shanbhag
University of Illinois at Urbana-Champaign, USA
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Massimo Poncino
Politecnico di Torino, Italy
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Pai H. Chou
University of California, Irvine / NTHU
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Ajith Amerasekera
Texas Instruments, USA

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Li HPao CChen BTsai C(2013)AOT-controlled dual-mode AVP buck regulator with AEAF mechanismProceedings of the IEEE 2013 Custom Integrated Circuits Conference10.1109/CICC.2013.6658538(1-4)Online publication date: Sep-2013
https://doi.org/10.1109/CICC.2013.6658538
Yoshimoto SMiyano STakamiya MShinohara HKawaguchi HYoshimoto M(2013)A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structureProceedings of the IEEE 2013 Custom Integrated Circuits Conference10.1109/CICC.2013.6658537(1-4)Online publication date: Sep-2013
https://doi.org/10.1109/CICC.2013.6658537

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Full-VDD and near-threshold performance of 8T FinFET SRAM cells

Sub-10 nm FinFETs and Tunnel-FETs: from devices to systems

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