research-article

ASCIB: adaptive selection of cache indexing bits for removing conflict misses

Authors:

Polychronis Xekalakis,

Marcelo Cintra,

Manuel E. Acacio,

José M. GarcíaAuthors Info & Claims

ISLPED '12: Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design

Pages 51 - 56

https://doi.org/10.1145/2333660.2333674

Published: 30 July 2012 Publication History

Abstract

The design of cache memories is a crucial part of the design cycle of a modern processor. Unfortunately, caches with low degrees of associativity suffer a large amount of conflict misses, while high-associative caches consume more power per access. We propose ASCIB, a simple technique able to dynamically adjust the bits used for cache indexing so as to minimize conflict misses. By selecting at run time the bits that disperse the working set more evenly across the available sets, ASCIB removes 73% of the conflict misses on average. This results in an improvement in energy efficiency by 17% on average.

References

[1]

A. Agarwal and S. D. Pudar. Column-associative caches: A technique for reducing the miss rate of direct-mapped caches. In 20st Int'l Symp. on Computer Architecture (ISCA), pages 179--190, May 1993.

Digital Library

[2]

K. Chaudhary, P. D. Costello, and V. M. Kondapalli. Programmable circuit optionally configurable as a lookup table or a wide multiplexer. U.S. Patent 7075333, Nov. 2006.

[3]

B.-K. Chung and J.-K. Peir. LRU-based column-associative caches. Computer Architecture News, 26(2):9--17, May 1998.

Digital Library

[4]

T. Givargis. Improved indexing for cache miss reduction in embedded systems. In 40th Design Automation Conference (DAC), pages 875--880, June 2003.

Digital Library

[5]

A. González, M. Valero, N. Topham, and J. M. Parcerisa. Eliminating cache conflict misses through XOR-based placement functions. In 11th Int'l Conference on Supercomputing (ICS), pages 76--83, June 1997.

Digital Library

[6]

M. D. Hill and A. J. Smith. Evaluating associativity in CPU caches. IEEE Transactions on Computers (TC), 38(12):1612--1630, Dec. 1989.

Digital Library

[7]

M. Kharbutli, K. Irwin, Y. Solihin, and J. Lee. Using prime numbers for cache indexing to eliminate conflict misses. In 11th Int'l Symp. on High-Performance Computer Architecture (HPCA), pages 288--299, Feb. 2004.

Digital Library

[8]

P. S. Magnusson, M. Christensson, and J. Eskilson, et al. Simics: A full system simulation platform. IEEE Computer, 35(2):50--58, Feb. 2002.

Digital Library

[9]

M. M. Martin, D. J. Sorin, and B. M. Beckmann, et al. Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset. Computer Architecture News, 33(4):92--99, Sept. 2005.

Digital Library

[10]

J.-K. Peir, Y. Lee, and W. W. Hsu. Capturing dynamic memory reference behavior with adaptive cache topology. In 8th Int'l Conf. on Architectural Support for Programming Language and Operating Systems (ASPLOS), pages 240--250, Oct. 1998.

Digital Library

[11]

M. K. Qureshi, D. Thompson, and Y. N. Patt. The v-way cache: Demand based associativity via global replacement. In 32nd Int'l Symp. on Computer Architecture (ISCA), pages 544--555, June 2005.

Digital Library

[12]

B. R. Rau. Pseudo-randomly interleaved memory. In 18th Int'l Symp. on Computer Architecture (ISCA), pages 74--83, June 1991.

Digital Library

[13]

D. Rolán, B. B. Fraguela, and R. Doallo. Adaptive line placement with the set balancing cache. In 42nd IEEE/ACM Int'l Symp. on Microarchitecture (MICRO), pages 529--540, Dec. 2009.

Digital Library

[14]

A. Seznec. A case for two-way skewed-associative caches. In 20st Int'l Symp. on Computer Architecture (ISCA), pages 169--178, May 1993.

Digital Library

[15]

Standard Performance Evaluation Corporation. SPEC CPU2006. http://www.spec.org/cpu2006.

[16]

S. Thoziyoor, N. Muralimanohar, J. H. Ahn, and N. P. Jouppi. Cacti 5.1. Technical Report HPL-2008--20, HP Labs, Apr. 2008.

[17]

C. Zhang. Balanced cache: Reducing conflict misses of direct-mapped caches. In 33rd Int'l Symp. on Computer Architecture (ISCA), pages 155--166, June 2006.

Digital Library

[18]

C. Zhang, X. Zhang, and Y. Yan. Two fast and high-associativity cache schemes. 17(5):40--49, Sept. 1998.

Digital Library

Cited By

Kim KPark JBaek W(2019)Improving the Performance and Energy Efficiency of GPGPU Computing through Integrated Adaptive Cache ManagementIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2018.286865830:3(630-645)Online publication date: 1-Mar-2019
https://doi.org/10.1109/TPDS.2018.2868658
Lotfi ASaxena NBramley RRacunas PShirvani P(2018)Low Overhead Tag Error Mitigation for GPU Architectures2018 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)10.1109/DSN.2018.00041(314-321)Online publication date: Jun-2018
https://doi.org/10.1109/DSN.2018.00041
(2017)A Review of Techniques for Optimizing Cache Energy EfficiencyVFAST Transactions on Software Engineering10.21015/vtse.v12i2.501(29-35)Online publication date: 1-May-2017
https://doi.org/10.21015/vtse.v12i2.501
Show More Cited By

Index Terms

ASCIB: adaptive selection of cache indexing bits for removing conflict misses
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

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Published In

cover image ACM Conferences

ISLPED '12: Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design

July 2012

438 pages

ISBN:9781450312493

DOI:10.1145/2333660

General Chairs:
Naresh Shanbhag
University of Illinois at Urbana-Champaign, USA
,
Massimo Poncino
Politecnico di Torino, Italy
,
Program Chairs:
Pai H. Chou
University of California, Irvine / NTHU
,
Ajith Amerasekera
Texas Instruments, USA

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 30 July 2012

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ISLPED'12

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SIGDA

ISLPED'12: International Symposium on Low Power Electronics and Design

July 30 - August 1, 2012

California, Redondo Beach, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

Kim KPark JBaek W(2019)Improving the Performance and Energy Efficiency of GPGPU Computing through Integrated Adaptive Cache ManagementIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2018.286865830:3(630-645)Online publication date: 1-Mar-2019
https://doi.org/10.1109/TPDS.2018.2868658
Lotfi ASaxena NBramley RRacunas PShirvani P(2018)Low Overhead Tag Error Mitigation for GPU Architectures2018 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)10.1109/DSN.2018.00041(314-321)Online publication date: Jun-2018
https://doi.org/10.1109/DSN.2018.00041
(2017)A Review of Techniques for Optimizing Cache Energy EfficiencyVFAST Transactions on Software Engineering10.21015/vtse.v12i2.501(29-35)Online publication date: 1-May-2017
https://doi.org/10.21015/vtse.v12i2.501
Choo KTroendle DGad EJang B(2017)Contention-Aware Selective Caching to Mitigate Intra-Warp Contention on GPUs2017 16th International Symposium on Parallel and Distributed Computing (ISPDC)10.1109/ISPDC.2017.17(1-8)Online publication date: Jul-2017
https://doi.org/10.1109/ISPDC.2017.17
Sembrant AHagersten EBlack-Schaffer D(2017)A Split Cache Hierarchy for Enabling Data-Oriented Optimizations2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2017.25(133-144)Online publication date: Feb-2017
https://doi.org/10.1109/HPCA.2017.25
Kim KPark JBaek W(2016)IACM: Integrated adaptive cache management for high-performance and energy-efficient GPGPU computing2016 IEEE 34th International Conference on Computer Design (ICCD)10.1109/ICCD.2016.7753308(380-383)Online publication date: Oct-2016
https://doi.org/10.1109/ICCD.2016.7753308
Wang BLiu ZWang XYu WNebel WAtienza D(2015)Eliminating intra-warp conflict misses in GPUProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2755911(689-694)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2755911
Kim KKim SBaek WEbrahimi MGoehringer D(2015)On the Feasibility of Advanced Cache Indexing for High-Performance and Energy-Efficient GPGPU ComputingProceedings of the 3rd International Workshop on Many-core Embedded Systems10.1145/2768177.2768179(1-8)Online publication date: 13-Jun-2015
https://dl.acm.org/doi/10.1145/2768177.2768179
Valls JSahuquillo JRos AGómez M(2015)The Tag Filter CacheProceedings of the 2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing10.1109/PDP.2015.58(182-189)Online publication date: 4-Mar-2015
https://dl.acm.org/doi/10.1109/PDP.2015.58
Ros AXekalakis PCintra MAcacio MGarcia J(2014)Adaptive Selection of Cache Indexing Bits for Removing Conflict MissesIEEE Transactions on Computers10.1109/TC.2014.2339819(1-1)Online publication date: 2014
https://doi.org/10.1109/TC.2014.2339819
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