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Evaluation of design alternatives for a multiprocessor microprocessor

Published: 01 May 1996 Publication History

Abstract

In the future, advanced integrated circuit processing and packaging technology will allow for several design options for multiprocessor microprocessors. In this paper we consider three architectures: shared-primary cache, shared-secondary cache, and shared-memory. We evaluate these three architectures using a complete system simulation environment which models the CPU, memory hierarchy and I/O devices in sufficient detail to boot and run a commercial operating system. Within our simulation environment, we measure performance using representative hand and compiler generated parallel applications, and a multiprogramming workload. Our results show that when applications exhibit fine-grained sharing, both shared-primary and shared-secondary architectures perform similarly when the full costs of sharing the primary cache are included.

References

[1]
S.P. Amarasinghe, J. M. Anderson, M. S. Lam, and C.-W. Tseng, "An overview of the SUIF compiler for scalable parallel machines," Proceedings of the Seventh SIAM Conference on Parallel Processing for Scientific Compiler, San Francisco, 1995.
[2]
S. Amarasinghe et.al., "Hot compilers for future hot chips," presented at Hot Chips VII, Stanford, CA, 1995.
[3]
J. Archibald and J. Baer "Cache coherence protocols: Evaluation using a multiprocessor simulation model," ACM Trans. on Computer Systems, Vol 4, no 4, pp. 273- 298.
[4]
J. Bennett and M. Fly-an, "Performance factors for superscalar processors," Technical report CSL-TR-95-661, Computer Systems Laboratory, Stanford University, February 1995.
[5]
Z. Cvetanovic and D. Bhandarkar, "Characterization of Alpha AXP performance using TP and SPEC workloads", Proc. 21st Annual Int. Symp. Computer Architecture, Chicago, pp. 60-69, 1994.
[6]
DECchip 21064A Hardware Reference Manual, Digital Equipment Corporation, Maynard, Massachusetts, 1994.
[7]
D. Fenwick, D. Foley, W. Gist, S. VanDoren, and D. Wissell, "The AlphaServer 8000 Series: high-end server platform development," Digital Technical Journal, vol. 7, pp. 43- 65, 1995.
[8]
M. FiUo, S. W. Keckler, W. j. Dally, N. P. Carter, A. Chang, Y. Gurevich, and W. S. Lee, "The M-Machine multicomputer," Proc. 28th Annual IEEE/A CM International Symp. on Microarchitecture, December 1995.
[9]
M. Galles, "The Challenge Interconnect: Design of a 1.2 GB/ s coherent mulfiprocessor bus," in Hot Interconnects, Stanford, CA, pp. 1.1.1-1.1.7, 1993
[10]
J. Goodman, "Cache Memories and Mulfiprocessors-- Tutorial Notes," in Third Int. Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS), Boston, MA, 1989.
[11]
J.L. Hennessy and D. A. Patterson, Computer Architecture A Quantitative Approach, 2nd ed, Morgan Kaufman Publishers, Inc., San Mateo, California, 1996.
[12]
P. Lacroute, "Real-time volume rendering on shared memory multiprocessors using the shear-warp factorization," 1995 Parallel Rendering Symposium,1995.
[13]
D. Kroft, "Loekup-free instruction fetch/prefetch cache organization," in Proc. 8th Annual Int. Symp. Computer Arehitocturo, pp. 81-87, 1981.
[14]
J. McDonald and D. Baganoff, "Vectorization of a particle simulation method for hypersonic rarefied flow," AIAA Thermodynamics, Plasma dynamics and Lasers
[15]
B.A. Nayfeh and K. Olukotun, "Exploring the Design Space for a Shared-Cache Multiprocessor," 21st Annual Int. Symp. Computer Architecture, Chicago, pp. 166-175 1994.
[16]
B.A. Nayfeh, K. Olukotun and J. P. Singh, "The Impact of Shared-Cache Clustering in Small-Scale Shared-Memory Mulfiprocessors",Proceedings of the Second Annual Symposium on High-Performance Computer Architecture, San Jose, CA. February 1996.
[17]
K. Olukotun, J. Bergmatm, and K. Chang, "Rationale and Design of the Hydra Multiprocessor," Computer Systems Laboratory Technical Report CSL-TR-94-645, Stanford University, 1994.
[18]
J. Ousterhout, "Why aren't operating systems getting faster as fast as hardware?," Summer 1990 USENIX Conference, pp. 247-256, June 1990.
[19]
R10000 Users Manual, version 1.0, Silicon Graphics International. 1995.
[20]
M. Rosenblum, S. Herrod, E. Witchel, and A. Gupta, "The SimOS approach," IEEE Parallel and Distributed Technology, vol. 4, no. 3, 1995.
[21]
M. Rosenblum, E. Bugnion, S. Herrod, E. Witehel, and A. Gupta, "The impact of architectural trends on operating system performance," Proc. 15th A CM symposium on Operating Systems Principles, Colorado, 1995.
[22]
J.P. Singh, W.-D. Weber and A. Gupta, "SPLASH: Stanford Parallel Applications for Shared-Memory", Computer Architecture News, 20(1 ):5-44, March 1992.
[23]
G. Sohi, S. Breach, and T. Vijaykumar, "Multiscalar Processors," 22nd Annual Int. Symp. Computer Architecture, Santa Margherita, Italy, June 1995.
[24]
D. Tullsen, S. Eggers, and H. Levy, "Simultaneous multithreading: maximizing on-chip parallelism," 22nd Annual Int. Syrup. Computer Architecture, Santa Margherita, Italy, 1995.
[25]
E. Witehel and M. Rosenblum, "Embra: fast and flexible machine simulation," A CM SIGMETRICS '96 Conference on Measurement and Modeling of Computer Systems, Philadelphia, 1996.
[26]
S.C. Woo, M. Ohara, E. Torrie, J.P. Singh and A. Gupta, "The SPLASH-2 Programs: Characterization and Methodological Considerations", 22nd Annual Int. Syrup. Computer Architecture, Santa Margherita, Italy, June 1995.
[27]
SPEC, "SPEC Benchmark Suite Release 2.0," System Performance Evaluation Cooperative, 1992.

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cover image ACM Conferences
ISCA '96: Proceedings of the 23rd annual international symposium on Computer architecture
May 1996
318 pages
ISBN:0897917863
DOI:10.1145/232973
  • cover image ACM SIGARCH Computer Architecture News
    ACM SIGARCH Computer Architecture News  Volume 24, Issue 2
    Special Issue: Proceedings of the 23rd annual international symposium on Computer architecture (ISCA '96)
    May 1996
    303 pages
    ISSN:0163-5964
    DOI:10.1145/232974
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Published: 01 May 1996

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May 22 - 24, 1996
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