Performance driven multiple-source bus synthesis using buffer insertion

In this paper, we propose a heuristic algorithm for a given topology of a multisource multisink bus to reduce the signal delay time. The algorithm minimizes the delay by inserting buffers into the candidate locations and sizing the buffers. When ...

Modern multi-processor system-on-chip (MPSoC) designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Bus matrix based communication architectures consist of several parallel busses, which provide a ...

Signal propagation delay on a multi-source multi-sink bidirectional bus has a dominant effect on high-performance chips. This work presents a novel greedy algorithm that minimizes the critical propagation delay of an RLC-based bus. Based on the topology ...