research-article

Exploiting narrow-width values for process variation-tolerant 3-D microprocessors

Authors:

Sung Woo ChungAuthors Info & Claims

DAC '12: Proceedings of the 49th Annual Design Automation Conference

Pages 1197 - 1206

https://doi.org/10.1145/2228360.2228581

Published: 03 June 2012 Publication History

Abstract

Process variation is a challenging problem in 3D microprocessors, since it adversely affects performance, power, and reliability of 3D microprocessors, which in turn results in yield losses. In this paper, we propose a novel architectural scheme that exploits the narrow-width value for yield improvement of last-level caches in 3D microprocessors. In a energy-/performance-efficient manner, our proposed scheme improves cache yield by 58.7% and 17.3% compared to the baseline and the naïve way-reduction scheme (that simply discards faulty cache lines), respectively.

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Cited By

Kong JHur J(2020)Near-Threshold L1 Data Cache for Yield Management Under Process VariationsIEEE Access10.1109/ACCESS.2020.29686038(18558-18570)Online publication date: 2020
https://doi.org/10.1109/ACCESS.2020.2968603
Jang JMin BKim C(2019)Denoised Residual Trace Analysis for Monitoring Semiconductor Process FaultsIEEE Transactions on Semiconductor Manufacturing10.1109/TSM.2019.291637432:3(293-301)Online publication date: Aug-2019
https://doi.org/10.1109/TSM.2019.2916374
Wang SDuan GLi YDong Q(2017)Word- and Partition-Level Write Variation Reduction for Improving Non-Volatile Cache LifetimeACM Transactions on Design Automation of Electronic Systems10.1145/308469023:1(1-18)Online publication date: 1-Aug-2017
https://dl.acm.org/doi/10.1145/3084690
Show More Cited By

Index Terms

Exploiting narrow-width values for process variation-tolerant 3-D microprocessors
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

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On the exploitation of narrow-width values for improving register file reliability

Protecting the register value and its data buses is crucial to reliable computing in high-performance microprocessors due to the increasing susceptibility of CMOS circuitry to soft errors induced by high-energy particle strikes. Since the register file ...
Word- and Partition-Level Write Variation Reduction for Improving Non-Volatile Cache Lifetime

Non-volatile memory technologies are among the most promising technologies for implementing the main memories and caches in future microprocessors and replacing the traditional DRAM and SRAM technologies. However, one of the most challenging design ...

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Published In

cover image ACM Conferences

DAC '12: Proceedings of the 49th Annual Design Automation Conference

June 2012

1357 pages

ISBN:9781450311991

DOI:10.1145/2228360

General Chair:
Patrick Groeneveld
Magma Design Automation, Inc., San Jose, CA
,
Program Chairs:
Donatella Sciuto
Politecnico di Milano, Milano, Italy
,
Soha Hassoun
Tufts Univ., Medford, MA

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

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SIGBED: ACM Special Interest Group on Embedded Systems

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 03 June 2012

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Ministry of Education, Science and Technology

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DAC '12

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EDAC
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DAC '12: The 49th Annual Design Automation Conference 2012

June 3 - 7, 2012

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Citations

Cited By

Kong JHur J(2020)Near-Threshold L1 Data Cache for Yield Management Under Process VariationsIEEE Access10.1109/ACCESS.2020.29686038(18558-18570)Online publication date: 2020
https://doi.org/10.1109/ACCESS.2020.2968603
Jang JMin BKim C(2019)Denoised Residual Trace Analysis for Monitoring Semiconductor Process FaultsIEEE Transactions on Semiconductor Manufacturing10.1109/TSM.2019.291637432:3(293-301)Online publication date: Aug-2019
https://doi.org/10.1109/TSM.2019.2916374
Wang SDuan GLi YDong Q(2017)Word- and Partition-Level Write Variation Reduction for Improving Non-Volatile Cache LifetimeACM Transactions on Design Automation of Electronic Systems10.1145/308469023:1(1-18)Online publication date: 1-Aug-2017
https://dl.acm.org/doi/10.1145/3084690
Imani MPatil SRosing TCoskun AMargala MBehjat LHan J(2016)DCCProceedings of the 26th edition on Great Lakes Symposium on VLSI10.1145/2902961.2902990(113-116)Online publication date: 18-May-2016
https://dl.acm.org/doi/10.1145/2902961.2902990
Mittal S(2016)A Survey of Architectural Techniques for Managing Process VariationACM Computing Surveys10.1145/287116748:4(1-29)Online publication date: 9-Feb-2016
https://dl.acm.org/doi/10.1145/2871167
Kong JKoushanfar FChung S(2015)An Energy-Efficient Last-Level Cache Architecture for Process Variation-Tolerant 3D MicroprocessorsIEEE Transactions on Computers10.1109/TC.2014.237829164:9(2460-2475)Online publication date: 1-Sep-2015
https://doi.org/10.1109/TC.2014.2378291
Roy PWang JWong W(2015)PAC: Program Analysis for Approximation-aware Compilation2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)10.1109/CASES.2015.7324547(69-78)Online publication date: Oct-2015
https://doi.org/10.1109/CASES.2015.7324547
Duan GWang SFettweis GNebel W(2014)Exploiting narrow-width values for improving non-volatile cache lifetimeProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616670(1-4)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616670
Kong JKoushanfar F(2014)Processor-Based Strong Physical Unclonable Functions With Aging-Based Response TuningIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2013.22893852:1(16-29)Online publication date: Mar-2014
https://doi.org/10.1109/TETC.2013.2289385
Kong JChung S(2013)Process variation-tolerant 3D microprocessor design: An efficient architectural solutionProceedings of 2013 International Conference on IC Design & Technology (ICICDT)10.1109/ICICDT.2013.6563300(45-48)Online publication date: May-2013
https://doi.org/10.1109/ICICDT.2013.6563300

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