research-article

A static-switching pulse domino technique for statistical power reduction of wide fan-in dynamic gates

Authors:

Suhwan KimAuthors Info & Claims

GLSVLSI '11: Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI

Pages 127 - 132

https://doi.org/10.1145/1973009.1973036

Published: 02 May 2011 Publication History

Get Access

Abstract

In wide fan-in dynamic domino gates, the two phase evaluate-precharge operation leads to high switching activity at the dynamic and the output nodes which introduces a significant power penalty. In this paper, we propose a pulse domino technique to reduce the overall power consumption of a wide fan-in dynamic gate by having static-like switching behavior at the dynamic node, the gate input and the output terminals. Dynamic multiplexers designed and simulated in 90-nm CMOS are used to demonstrate the energy effectiveness of the proposed design style.

References

[1]

K. L. Shepard and V. Narayanan, "Noise in deep submicron digital design," in Proc. IEEE Int. ASIC/SOC Conf., 1996, pp. 524--531.

Digital Library

Google Scholar

[2]

K. Bernstein, K. M. Carrig, C. M. Durham, P. R. Hansen, D. Hogenmiller, E. J. Nowak, and N. J. Rohrer, High Speed CMOS Design Styles, Kluwer Academic Publishers, 1999.

Digital Library

Google Scholar

[3]

C. J. Akl and M. A. Bayoumi, "Single-Phase SP-domino: a limited-switching dynamic circuit technique for low-power wide fan-in logic gates," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 2, pp. 141--145, Feb. 2008.

Crossref

Google Scholar

[4]

R. Montoye, et al., "A double precision floating point multiply," in Proc. IEEE Int. Solid-State Circuits Conf., 2003, pp. 336--337.

Google Scholar

[5]

J. Sivagnaname, H.C. Ngo, K. J. Nowka, R. K. Montoye, and R. B. Brown, "Wide limited switch dynamic logic implementations," in Proc. IEEE Int. Conf. on VLSI Design, 2006.

Digital Library

Google Scholar

[6]

G. Yee and C. Sechen, "Clock-delayed domino for dynamic circuit design," IEEE Trans. Very Large-Scale Integr. (VLSI) Syst., vol. 8, no. 4, pp. 425--430, Aug. 2000.

Digital Library

Google Scholar

[7]

H. Mahmoodi-Meimand and K. Roy, "Diode-footed domino: a leakage-tolerant high fan-in dynamic circuit design," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 3, pp. 495--503, Mar. 2004.

Crossref

Google Scholar

Cited By

View all

Singh RHong GKim MPark JShin WKim S(2018)Static-switching pulse dominoIntegration, the VLSI Journal10.1016/j.vlsi.2011.11.01345:3(253-262)Online publication date: 28-Dec-2018
https://dl.acm.org/doi/10.1016/j.vlsi.2011.11.013
Singh RHong GKim S(2013)Bitline Techniques With Dual Dynamic Nodes for Low-Power Register FilesIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2012.222045760:4(965-974)Online publication date: Apr-2013
https://doi.org/10.1109/TCSI.2012.2220457

Index Terms

A static-switching pulse domino technique for statistical power reduction of wide fan-in dynamic gates
1. Hardware
  1. Integrated circuits
    1. Logic circuits
      1. Combinational circuits

Recommendations

Static-switching pulse domino: A switching-aware design technique for wide fan-in dynamic multiplexers

In wide fan-in dynamic multiplexers, the two phase evaluate-precharge operation leads to high switching activity at the dynamic and the output nodes introducing a significant power penalty. To address this issue, the switching-aware design techniques ...
New partitioned domino circuit for power-efficient wide gates
Abstract
In this article, a new domino circuit is presented to decrease the power consumption of wide gates without considerable performance and robustness degradation. The suggested circuit technique modifies the output inverter to decrease ...
Highlights
- A new high-speed and low power domino logic circuit is proposed for wide gates.
A high speed and leakage-tolerant domino logic for high fan-in gates
GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

Robustness of high fan-in domino circuits is degraded by technology scaling due to exponential increase in leakage. In this paper, we propose a new domino circuit for high fan-in and high-speed applications in ultra deep submicron technologies. The ...

Comments

Information & Contributors

Information

Published In

GLSVLSI '11: Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI

May 2011

496 pages

ISBN:9781450306676

DOI:10.1145/1973009

General Chairs:
David Atienza
EPFL, Switzerland
,
Yuan Xie
Penn State University, USA
,
Program Chairs:
Jose L. Ayala
Federal University of Pernambuco, Brazil
,
Ken Stevens
University of Utah, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

In-Cooperation

IEEE CEDA
IEEE CASS

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 02 May 2011

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

GLSVLSI '11

Sponsor:

SIGDA

GLSVLSI '11: Great Lakes Symposium on VLSI 2011

May 2 - 4, 2011

Lausanne, Switzerland

Acceptance Rates

Overall Acceptance Rate 312 of 1,156 submissions, 27%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

2
Total Citations
View Citations
118
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 06 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Singh RHong GKim MPark JShin WKim S(2018)Static-switching pulse dominoIntegration, the VLSI Journal10.1016/j.vlsi.2011.11.01345:3(253-262)Online publication date: 28-Dec-2018
https://dl.acm.org/doi/10.1016/j.vlsi.2011.11.013
Singh RHong GKim S(2013)Bitline Techniques With Dual Dynamic Nodes for Low-Power Register FilesIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2012.222045760:4(965-974)Online publication date: Apr-2013
https://doi.org/10.1109/TCSI.2012.2220457

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Static-switching pulse domino: A switching-aware design technique for wide fan-in dynamic multiplexers

New partitioned domino circuit for power-efficient wide gates

A high speed and leakage-tolerant domino logic for high fan-in gates