research-article

The RLOC is dead - long live the RLOC

Author:

Satnam SinghAuthors Info & Claims

FPGA '11: Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays

Pages 185 - 188

https://doi.org/10.1145/1950413.1950450

Published: 27 February 2011 Publication History

Get Access

Abstract

Are user specified layout constraints of significant value anymore? Certainly in the past the use of the RLOC layout constraint for Xilinx FPGAs was essential for achieving the best possible performance for many kinds of highly structured designs. However, have CAD tools evolved to the point where they can always compute layouts as good as (if not better than) humans? Or has the introduction of on-chip hard cores, which create an irregular 2D surface for layouts, made layout specification impractical? Or has the varying pitch and types of combinational logic blocks (CLBs) made it intractable to produce layout descriptions that are portable across architectures? We show that the use of layout constraints still delivers a large performance gain for Xilinx's recent Virtex-6 family of FPGAs. The performance gain is sometime large enough to accommodate a reduction of two speed grades.

References

[1]

Hannah Bian, Andrew Ling, Jianwen Zhu, Alexander Choong, "Towards Scalable Placement for FPGAs", IEEE Symposium on FPGAs. 2010.

Digital Library

Google Scholar

[2]

K. E. Batcher, "Sorting networks and their applications," In AFIPS Spring Joint Computing Conference, volume 32, 1969.

Digital Library

Google Scholar

[3]

Per Bjesse, Koen Claessen, Mary Sheeran, Satnam Singh, "Lava: Hardware Design in Haskell," ICFP'98. Springer-Verlag LNCS, 1998.

Digital Library

Google Scholar

[4]

Saar Drimer, "The Meaning and Reproducibility of FPGA Results", Chapter 5, PhD Thesis, "Security for Volatile FPGAs." The University of Cambridge. November, 2009.

Google Scholar

[5]

Peter Henderson, "Functional Geometry", Higher Order and Symbolic Computation, 15(4), 2002.

Digital Library

Google Scholar

[6]

Jason Lee and Lesley Shannon, "Predicting the Performance of Application-Specific NoCs Implemented on FPGAs", IEEE Symposium on FPGAs. 2010.

Digital Library

Google Scholar

[7]

René Müller, Jens Teubner, Gustavo Alonso, "Streams on Wires: A Query Compiler for FPGAs", In Proceedings of the VLDB Endowment, Vol 2, No. 1--2, 2009. (VLDB 2009), Lyon, France.

Digital Library

Google Scholar

[8]

René Müller, Jens Teubner, Gustavo Alonso, "Data Processingon FPGAs", In Proceedings of the VLDB Endowment, Vol 2, No. 1--2, 2009. (VLDB 2009), Lyon, France.

Digital Library

Google Scholar

[9]

Rishiyur Nikhil, "Bluespec SystemVerilog: Efficient, correct RTL from high-level specifications," Formal Methods and Models for Co-Design (MEMOCODE), 2004.

Google Scholar

[10]

Yi Shan, Bo Wang, Jing Yan, Yu Wang, Ningyi Xu2, Huazhong Yang, "FPMR : MapReduce Framework on FPGA - a Case Study of RankBoost Acceleration", IEEE Symposium on FPGAs. 2010.

Digital Library

Google Scholar

[11]

Satnam Singh, "Death of the RLOC?" IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), April 2000.

Digital Library

Google Scholar

[12]

Jens Teubner, René Müller, Gustavo Alonso, "FPGA Acceleration for the Frequent Item Problem", In Proceedings of the 26th Int'l Conference on Data Engineering (ICDE), Long Beach, CA, USA March 2010

Crossref

Google Scholar

[13]

Jackson H. C. Yeung, C. C. Tsang, K. H. Tsoi, Bill S. H. Kwan, Chris C. C. Cheung, Anthony P. C. Chan and Philip H. W. Leong, "Map-reduce as a Programming Model for Custom Computing Machins", IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), April 2008.

Digital Library

Google Scholar

Cited By

View all

Gammie P(2013)Synchronous digital circuits as functional programsACM Computing Surveys10.1145/2543581.254358846:2(1-27)Online publication date: 1-Nov-2013
https://dl.acm.org/doi/10.1145/2543581.2543588
Miller BVahid FGivargis THutchings BBetz V(2013)Embedding-based placement of processing element networks on FPGAs for physical model simulationProceedings of the ACM/SIGDA international symposium on Field programmable gate arrays10.1145/2435264.2435297(181-190)Online publication date: 11-Feb-2013
https://dl.acm.org/doi/10.1145/2435264.2435297
Burrows EHaveraaen MAcar UCosta V(2012)Programmable data dependencies and placementsProceedings of the 7th workshop on Declarative aspects and applications of multicore programming10.1145/2103736.2103741(31-40)Online publication date: 28-Jan-2012
https://dl.acm.org/doi/10.1145/2103736.2103741

Index Terms

The RLOC is dead - long live the RLOC
1. Computer systems organization

Recommendations

Death of the RLOC?
FCCM '00: Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines

“RLOC” is the name given to a relational placement macro that is used to influence the layout of circuits that are realized on FPGAs using Xilinx's place and route software. This paper explores the thesis that modern FPGA architectures are powerful ...
Performance-driven simultaneous place and route for island-style FPGAs
ICCAD '95: Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Abstract: Sequential place and route tools for FPGAs are inherently weak at addressing both wirability and timing optimizations. This is primarily due to the difficulty of accurately predicting wirability and delay during placement. A new performance-...
RLoc: Towards Robust Indoor Localization by Quantifying Uncertainty

In recent years, decimeter-level accuracy in WiFi indoor localization has become attainable within controlled environments. However, existing methods encounter challenges in maintaining robustness in more complex indoor environments: angle-based methods ...

Comments

Information & Contributors

Information

Published In

FPGA '11: Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays

February 2011

300 pages

ISBN:9781450305549

DOI:10.1145/1950413

General Chair:
John Wawrzynek
University of California, Berkeley, USA
,
Program Chair:
Katherine Compton
University of Wisconsin-Madison, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 27 February 2011

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tag

circuit layout

Qualifiers

Research-article

Conference

FPGA '11

Sponsor:

SIGDA

FPGA '11: ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 27 - March 1, 2011

CA, Monterey, USA

Acceptance Rates

Overall Acceptance Rate 125 of 627 submissions, 20%

Upcoming Conference

FPGA '25

Sponsor:
sigda

The 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 27 - March 1, 2025

Monterey , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

3
Total Citations
View Citations
284
Total Downloads

Downloads (Last 12 months)8
Downloads (Last 6 weeks)0

Reflects downloads up to 25 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Gammie P(2013)Synchronous digital circuits as functional programsACM Computing Surveys10.1145/2543581.254358846:2(1-27)Online publication date: 1-Nov-2013
https://dl.acm.org/doi/10.1145/2543581.2543588
Miller BVahid FGivargis THutchings BBetz V(2013)Embedding-based placement of processing element networks on FPGAs for physical model simulationProceedings of the ACM/SIGDA international symposium on Field programmable gate arrays10.1145/2435264.2435297(181-190)Online publication date: 11-Feb-2013
https://dl.acm.org/doi/10.1145/2435264.2435297
Burrows EHaveraaen MAcar UCosta V(2012)Programmable data dependencies and placementsProceedings of the 7th workshop on Declarative aspects and applications of multicore programming10.1145/2103736.2103741(31-40)Online publication date: 28-Jan-2012
https://dl.acm.org/doi/10.1145/2103736.2103741

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Abstract

References

Cited By

Index Terms

Recommendations

Death of the RLOC?

Performance-driven simultaneous place and route for island-style FPGAs

RLoc: Towards Robust Indoor Localization by Quantifying Uncertainty

Comments

Information

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Author Tag

Qualifiers

Conference

Acceptance Rates

Upcoming Conference

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

Login options

Full Access

View options

PDF

eReader

Share

Share this Publication link

Share on social media

Affiliations