research-article

RDE-based transistor-level gate simulation for statistical static timing analysis

Authors:

Michel Berkelaar,

Nick van der MeijsAuthors Info & Claims

DAC '10: Proceedings of the 47th Design Automation Conference

Pages 787 - 792

https://doi.org/10.1145/1837274.1837473

Published: 13 June 2010 Publication History

Abstract

Existing industry-practice statistical static timing analysis (SSTA) engines use black-box gate-level models for standard cells, which have accuracy problems as well as require massive amounts of CPU time in Monte-Carlo (MC) simulation. In this paper we present a new transistor-level non-Monte Carlo statistical analysis method based on solving random differential equations (RDE) computed from modified nodal analysis (MNA). In order to maintain both high accuracy and efficiency, we introduce a simplified statistical transistor model for 45nm technology and below. The model is combined with our new simulation-like engine which can do both implicit non-MC statistical simulation and deterministic simulation fast and accurately. The statistics of delay and slew are calculated by means of the proposed analysis method. Experiments show the proposed method is both run time efficient and very accurate.

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Cited By

Patil SGautam D(2018)Statistical Modeling of Combinational Circuits Using Path Based Delay AnalysisSilicon10.1007/s12633-017-9721-z10:5(2063-2069)Online publication date: 19-Mar-2018
https://doi.org/10.1007/s12633-017-9721-z
Tang QRodriguez JZjajo ABerkelaar Mvan der Meijs N(2014)Statistical Transistor-Level Timing Analysis Using a Direct Random Differential Equation SolverIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.228717933:2(210-223)Online publication date: Feb-2014
https://doi.org/10.1109/TCAD.2013.2287179
Zjajo AZjajo A(2013)Random Process Variation in Deep-Submicron CMOSStochastic Process Variation in Deep-Submicron CMOS10.1007/978-94-007-7781-1_2(17-54)Online publication date: 14-Nov-2013
https://doi.org/10.1007/978-94-007-7781-1_2
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Index Terms

RDE-based transistor-level gate simulation for statistical static timing analysis

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cover image ACM Conferences

DAC '10: Proceedings of the 47th Design Automation Conference

June 2010

1036 pages

ISBN:9781450300025

DOI:10.1145/1837274

General Chair:
Sachin Sapatnekar
Univ. of Minnesota, Minneapolis, MN

Copyright © 2010 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 June 2010

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DAC '10: The 47th Annual Design Automation Conference 2010

June 13 - 18, 2010

California, Anaheim

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Patil SGautam D(2018)Statistical Modeling of Combinational Circuits Using Path Based Delay AnalysisSilicon10.1007/s12633-017-9721-z10:5(2063-2069)Online publication date: 19-Mar-2018
https://doi.org/10.1007/s12633-017-9721-z
Tang QRodriguez JZjajo ABerkelaar Mvan der Meijs N(2014)Statistical Transistor-Level Timing Analysis Using a Direct Random Differential Equation SolverIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.228717933:2(210-223)Online publication date: Feb-2014
https://doi.org/10.1109/TCAD.2013.2287179
Zjajo AZjajo A(2013)Random Process Variation in Deep-Submicron CMOSStochastic Process Variation in Deep-Submicron CMOS10.1007/978-94-007-7781-1_2(17-54)Online publication date: 14-Nov-2013
https://doi.org/10.1007/978-94-007-7781-1_2
Rodríguez JTang QZjajo ABerkelaar Mvan der Meijs N(2013)Direct Statistical Simulation of Timing Properties in Sequential CircuitsIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation10.1007/978-3-642-36157-9_14(131-141)Online publication date: 2013
https://doi.org/10.1007/978-3-642-36157-9_14
Knoth CJedda HSchlichtmann URosenstiel WMacii E(2012)Current source modeling for power and timing analysis at different supply voltagesProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492940(923-928)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2492940
Tang QZjajo ABerkelaar Mvan der Meijs NRosenstiel WMacii E(2012)Transistor-level gate model based statistical timing analysis considering correlationsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492939(917-922)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2492939
Knoth CJedda HSchlichtmann U(2012)Current source modeling for power and timing analysis at different supply voltages2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.1109/DATE.2012.6176629(923-928)Online publication date: Mar-2012
https://doi.org/10.1109/DATE.2012.6176629
Qin Tang Zjajo ABerkelaar Mvan der Meijs N(2012)Transistor-level gate model based statistical timing analysis considering correlations2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.1109/DATE.2012.6176628(917-922)Online publication date: Mar-2012
https://doi.org/10.1109/DATE.2012.6176628
Knoth CUphoff CKiesel SSchlichtmann U(2011)SWATProceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation10.5555/2045364.2045384(193-203)Online publication date: 26-Sep-2011
https://dl.acm.org/doi/10.5555/2045364.2045384
Zjajo ATang QBerkelaar Mvan der Meijs N(2011)Accuracy consideration of a non-Gaussian interconnect delay model for submicron CMOS statistical static timing analysisThe 4th IEEE International NanoElectronics Conference10.1109/INEC.2011.5991680(1-2)Online publication date: Jun-2011
https://doi.org/10.1109/INEC.2011.5991680
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