Performance and power evaluation of an in-line accelerator
Authors: 
Alejandro Rico, 
Jeff H. Derby, Robert K. Montoye, Timothy H. Heil, 
Chen-Yong Cher, Pradip BoseAuthors Info & Claims
Alejandro Rico, Jeff H. Derby, Robert K. Montoye, Timothy H. Heil, Chen-Yong Cher, Pradip BoseAuthors Info & ClaimsPages 81 - 82
Abstract
In this paper we evaluate the performance and power of a processor-attached in-line accelerator. The accelerator provides high-performance SIMD computing and power efficiency by means of a very large register file and a set of vector multimedia extensions based on IBM's PowerPC VMX. Our experiments show significant performance improvements and power reduction, compared to a baseline vector execution unit, mainly due to the drastic decrease of memory accesses caused by the software-managed locality of the very large register file. Total execution time is, on average, reduced by 61%, while consuming 55% less energy.
References
[1]
J. H. Derby et al. VICTORIA: VMX indirect compute technology oriented towards in-line acceleration. In CF '06, pages 303--312, 2006.
[2]
L. Bachega et al. A High-Performance SIMD Floating Point Unit for BlueGene/L: Architecture, Compilation, and Algorithm Design. In PACT '04, pages 85--96, 2004.
Index Terms
- Performance and power evaluation of an in-line accelerator
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Information & Contributors
Information
Published In
May 2010
370 pages
ISBN:9781450300445
DOI:10.1145/1787275
- General Chair:
- Nancy M. Amato,
- Program Chairs:
- Hubertus Franke,
- Paul H.J. Kelly
Copyright © 2010 Copyright is held by the owner/author(s).
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Association for Computing Machinery
New York, NY, United States
Publication History
Published: 17 May 2010
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CF'10
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CF '10 Paper Acceptance Rate 30 of 113 submissions, 27%;
Overall Acceptance Rate 273 of 785 submissions, 35%
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CF '25
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