research-article

Design considerations for variation tolerant multilevel CMOS/Nano memristor memory

Authors:

Harika Manem,

Garrett S. Rose,

Xiaoli He,

Wei WangAuthors Info & Claims

GLSVLSI '10: Proceedings of the 20th symposium on Great lakes symposium on VLSI

Pages 287 - 292

https://doi.org/10.1145/1785481.1785548

Published: 16 May 2010 Publication History

Get Access

Abstract

With technology migration into nano and molecular scales several hybrid CMOS/nano logic and memory architectures have been proposed thus far that aim to achieve high device density with low power consumption. The discovery of the memristor has further enabled the realization of denser nanoscale logic and memory systems. This work describes the design of such a multilevel memristor memory (MLMM) system, and the design constraints imposed in the realization of such a memory. In particular, the limitations on load, bank size, number of bits achievable per device, placed by the required noise margin (NM) for accurately reading the data stored in a device are analyzed.

References

[1]

D. B. Strukov, G. S. Snider, D. R. Stewart, S. R. Williams, "The missing memristor found," Nature, vol. 453, no. 7191, pp.80--83, 2008.

Crossref

Google Scholar

[2]

G. S. Snider, "Memristors as synapses in a neural computing architecture," Memristor and Memristive systems Symposium, Nov 2008.

Google Scholar

[3]

A. Chen, S. Haddad, Y. C. Wu, T. N. Fang et al. "Non-volatile resistive switching for advanced memory applications," in Proc. Of IEEE Elec. Dev. Mtg., pp. 746--749, 2005.

Google Scholar

[4]

G. S. Rose, Y. Tao, J. M. Tour, M. R. Stan et al. "Designing CMOS/Molecular memories while considering device parameter variations," ACM Journal on Emerging Technologies and Computing Systems, vol. 3, no. 1, April 2007.

Digital Library

Google Scholar

[5]

R. Bez and A. Pirovano, "Non-volatile memory technologies: Emerging concepts and new materials," Materials Science in Semiconductor Processing, vol. 7, no. 4--6, pp. 349--355, 2004.

Google Scholar

[6]

S. Kim, Y. Zhang, B. Lee; M. Caldwell, H. -S. P. Wong, "Fabrication and characterization of emerging nanoscale memory," ISCAS, pp. 65--68, 2009.

Google Scholar

[7]

M. M. Ziegler and M. R. Stan, "Design and analysis of crossbar circuits for molecular nanoelectronics," In Proceedings of the IEEE Conference on Nanotechnology, 2002: pp. 323--327.

Google Scholar

[8]

J. R. Hauser, "Noise margin criteria for digital logic circuits," IEEE Trans. on Education, vol. 36, no. 4, pp. 363--368, Nov 1993.

Digital Library

Google Scholar

[9]

T. Ogura et al. "A 1.8-V 256-Mb Multilevel Cell NOR Flash Memory with BGO Function," IEEE Journal of Solid-State Circuits, vol. 41, pp. 2589--2600, 2006.

Crossref

Google Scholar

[10]

M. Bauer et al. "A Multilevel-Cell 32Mb Flash Memory," IEEE Int. Solid-State Circuits Conf., Digest of Technical Papers, pp. 132--133, 1995.

Google Scholar

[11]

S. Raoux, G. W. Burr, M. J. Breitwisch, C. T. Rettner, Y.-C. Chen, R. M. Shelby, M. Salinga, D. Krebs, S.-H. Chen, H.-L. Lung, and C. H. Lam, "Phase-change random access memory: A scalable technology," IBM J. Res. & Dev., vol. 52, No. 4/5, pp. 465--479, 2008.

Digital Library

Google Scholar

[12]

M. Liu, Z. Abid, W. Wang, X. He, Q. Liu, and W. Guan, "Multi-Level Resistive Switching with Ionic and Metallic Filaments," Applied Physics Letters, vol. 94, no. 23, id. 233106 (3 pages), 2009.

Google Scholar

[13]

Qi Liu, Chunmeng Dou, Yan Wang, Shibing Long, Wei Wang, et. al. "Formation of multiple conductive filaments in the Cu/ZrO2:Cu/Pt device," Applied Physics Letters, vol. 95, id. 023501, Jul. 2009.

Crossref

Google Scholar

[14]

W. Guan, M. Liu, S. Long, Q. Liu, and W. Wang, "On the resistive switching mechanisms of Cu/ZrO2:Cu/Pt," Applied Physics Letters, vol. 93, no. 22, id. 223506 (3 pages) Dec. 2008.

Crossref

Google Scholar

Cited By

View all

S SV R(2024)Review of memristor based neuromorphic computation: opportunities, challenges and applicationsEngineering Research Express10.1088/2631-8695/ad66626:3(032203)Online publication date: 7-Aug-2024
https://doi.org/10.1088/2631-8695/ad6662
Mondal MSur-Kolay SBhattacharya B(2023)Test Optimization in Memristor Crossbars Based on Path SelectionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.316878242:1(294-307)Online publication date: Jan-2023
https://doi.org/10.1109/TCAD.2022.3168782
Zhou XYu DLi ZYu SJunaid M(2023)A pulse train controlled Buck converter based on a single memristive multi-vibratorInternational Journal of Electronics10.1080/00207217.2023.2267211111:12(2219-2241)Online publication date: 17-Oct-2023
https://doi.org/10.1080/00207217.2023.2267211
Show More Cited By

Index Terms

Design considerations for variation tolerant multilevel CMOS/Nano memristor memory
1. Hardware

Recommendations

Design Considerations for Multilevel CMOS/Nano Memristive Memory

With technology migration into nano and molecular scales several hybrid CMOS/nano logic and memory architectures have been proposed that aim to achieve high device density with low power consumption. The discovery of the memristor has further enabled ...
A multilevel memristor-CMOS memory cell as a ReRAM

Memristor is a newly invented device and since it has been found, has drawn a lot of attention from integrated electronics designers because of its nanometer size and special electrical properties. One of the most significant characteristics of a ...
Variability-Tolerant Memristor-based Ratioed Logic in Crossbar Array
NANOARCH '18: Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures

The advent of the first TiO2-based memristor in 2008 revived the scientific interest both from academia and industry for this device technology, with several emerging applications including that of logic circuits. Several memristive logic families have ...

Comments

Information & Contributors

Information

Published In

GLSVLSI '10: Proceedings of the 20th symposium on Great lakes symposium on VLSI

May 2010

502 pages

ISBN:9781450300124

DOI:10.1145/1785481

General Chairs:
R. Iris Bahar
Brown University, USA
,
Fabrizio Lombardi
Northeastern University, USA
,
Program Chairs:
David Atienza
EPFL, Switzerland
,
Erik Brunvand
University of Utah, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

In-Cooperation

IEEE CEDA
IEEE CASS

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 16 May 2010

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

GLSVLSI '10

Sponsor:

SIGDA

GLSVLSI '10: Great Lakes Symposium on VLSI 2010

May 16 - 18, 2010

Rhode Island, Providence, USA

Acceptance Rates

Overall Acceptance Rate 312 of 1,156 submissions, 27%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

72
Total Citations
View Citations
1,314
Total Downloads

Downloads (Last 12 months)42
Downloads (Last 6 weeks)3

Reflects downloads up to 01 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

S SV R(2024)Review of memristor based neuromorphic computation: opportunities, challenges and applicationsEngineering Research Express10.1088/2631-8695/ad66626:3(032203)Online publication date: 7-Aug-2024
https://doi.org/10.1088/2631-8695/ad6662
Mondal MSur-Kolay SBhattacharya B(2023)Test Optimization in Memristor Crossbars Based on Path SelectionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.316878242:1(294-307)Online publication date: Jan-2023
https://doi.org/10.1109/TCAD.2022.3168782
Zhou XYu DLi ZYu SJunaid M(2023)A pulse train controlled Buck converter based on a single memristive multi-vibratorInternational Journal of Electronics10.1080/00207217.2023.2267211111:12(2219-2241)Online publication date: 17-Oct-2023
https://doi.org/10.1080/00207217.2023.2267211
Sadi MSumon MAli M(2023)Soft Error Tolerant Memristor-Based MemoryProceedings of International Conference on Information and Communication Technology for Development10.1007/978-981-19-7528-8_33(421-434)Online publication date: 26-Jan-2023
https://doi.org/10.1007/978-981-19-7528-8_33
Wang SYuan GMa XLi YLin XKailkhura B(2022)Fault-Tolerant Deep Neural Networks for Processing-In-Memory based Autonomous Edge Systems2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE54114.2022.9774523(424-429)Online publication date: 14-Mar-2022
https://doi.org/10.23919/DATE54114.2022.9774523
Sumon MAli MSadi M(2022)An Efficient Triple-Error Correction Method for Memristor-Based Memory Systems2022 12th International Conference on Electrical and Computer Engineering (ICECE)10.1109/ICECE57408.2022.10088479(380-383)Online publication date: 21-Dec-2022
https://doi.org/10.1109/ICECE57408.2022.10088479
Saleh SKoldehofe B(2022)On Memristors for Enabling Energy Efficient and Enhanced Cognitive Network FunctionsIEEE Access10.1109/ACCESS.2022.322644710(129279-129312)Online publication date: 2022
https://doi.org/10.1109/ACCESS.2022.3226447
Mohajeri NEbrahimi BDousti M(2021)HPM: High-Precision Modeling of a Low-Power Inverter-Based Memristive Neural NetworkJournal of Circuits, Systems and Computers10.1142/S021812662150274130:15Online publication date: 26-May-2021
https://doi.org/10.1142/S0218126621502741
Yuan GLiao ZMa XCai YKong ZShen XFu JLi ZZhang CPeng HLiu NRen AWang JWang Y(2021)Improving DNN Fault Tolerance using Weight Pruning and Differential Crossbar Mapping for ReRAM-based Edge AI2021 22nd International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED51717.2021.9424332(135-141)Online publication date: 7-Apr-2021
https://doi.org/10.1109/ISQED51717.2021.9424332
Isyaku UKhir MNawi IZakariya MZahoor F(2021)ZnO Based Resistive Random Access Memory Device: A Prospective Multifunctional Next-Generation MemoryIEEE Access10.1109/ACCESS.2021.30980619(105012-105047)Online publication date: 2021
https://doi.org/10.1109/ACCESS.2021.3098061
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Design Considerations for Multilevel CMOS/Nano Memristive Memory

A multilevel memristor-CMOS memory cell as a ReRAM

Variability-Tolerant Memristor-based Ratioed Logic in Crossbar Array