A delay measurement method using a shrinking clock signal
Pages 139 - 142
Abstract
This paper describes a delay measurement method using a shrinking clock signal. The shrinking clock is generated from an AND operation on two clock signals having slightly different periods, which are provided by an external tester. Instead of measuring the number of clocks before it vanishes, another AND operation is utilized to reduce the size of the counter. A differential approach is used to minimize the effect from any non-ideal behavior of circuits used for the measurement as well as to substitute for calibration. In the proposed method, the dynamic range, the measurement resolution and accuracy do not depend on the measurement circuit itself, but on the external clocks from the tester. Circuit-level simulations show good linearity and measurement accuracy regardless of process, voltage, and temperature (PVT) variations when the edge placement accuracy of the external tester amounts to 100ps.
References
[1]
Semi draft doc. #2928: Specification for overall digital timing accuracy. Technical report, Semiconductor Equipment and Materials International, 1999.
[2]
P. Chen, S.-I. Liu, and J. Wu. A low power high accuracy CMOS time-to-digital converter. In Proceedings, IEEE International Symposium on Circuits and Systems (ISCAS '97), vol. 1, pages 281--284, June 1997.
[3]
W. Dalal and S. Miao. The value of tester accuracy. In Proceedings, International Test Conference, pages 518--523, 1999.
[4]
R. Datta, G. Carpenter, K. Nowka, and J. Abraham. A scheme for on-chip timing characterization. In Proceedings, 24th IEEE VLSI Test Symposium, 31 April -- 4 May 2006.
[5]
D. Keezer, D. Minier, and P. Ducharme. Method for reducing jitter in multi-gigahertz ATE. In Design, Automation & Test in Europe Conference & Exhibition (DATE '07), April 2007.
[6]
I. Park, D. Lee, E. Chmelar, and E. McCluskey. Inconsistent fail due to limited tester timing accuracy. In 26th IEEE VLSI Test Symposium (VTS 2008), pages 47--52, 27 April -- May 1 2008.
[7]
T. Rahkonen and J. Kostamovaara. Pulsewidth measurements using an integrated pulse shrinking delay line. In IEEE International Symposium on Circuits and Systems, vol. 1, pages 578--581, May 1990.
Index Terms
- A delay measurement method using a shrinking clock signal
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Published In
May 2010
502 pages
ISBN:9781450300124
DOI:10.1145/1785481
- General Chairs:
- R. Iris Bahar,
- Fabrizio Lombardi,
- Program Chairs:
- David Atienza,
- Erik Brunvand
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Published: 16 May 2010
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