research-article

An elegant hardware-corroborated statistical repair and test methodology for conquering aging effects

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Sani NassifAuthors Info & Claims

ICCAD '09: Proceedings of the 2009 International Conference on Computer-Aided Design

Pages 497 - 504

https://doi.org/10.1145/1687399.1687494

Published: 02 November 2009 Publication History

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Abstract

We propose a new and efficient statistical-simulation-based test methodology for optimally selecting repair elements at beginning-of-life (BOL) to improve the end-of-life (EOL) functionality of memory designs. This is achieved by identifying the best BOL test/repair corner that maximizes EOL yield, thereby exploiting redundancy to optimize EOL operability with minimal BOL yield loss. The statistical approach makes it possible to identify such corners with tremendous savings in terms of test time and hardware. To estimate yields and search for the best repair corner the approach relies on fast conditional importance sampling statistical simulations. The methodology is versatile and can handle complex aging effects with asymmetrical distributions. Results are demonstrated on state-of-the-art dual-supply memory designs subject to statistical negative bias temperature instability (NBTI) effects, and hardware results are shown to match predicted model trends.

References

[1]

S. R. Nassif, "Design for variability in DSM technologies", ISQED, 2000, pp. 451--454

Digital Library

Google Scholar

[2]

V. De, and S. Borkar, "Technology and design challenges for low power and high performance", ISLPED '99, pp. 163--168.

Digital Library

Google Scholar

[3]

R. V. Joshi et al., "A low power and high-performance SOI SRAM circuit design with improved cell stability", SOI Conf. 2006, pp. 211--214.

Crossref

Google Scholar

[4]

R. V. Joshi et al., "Variability analysis for Sub-100 nm PD/SOI CMOS SRAM cell", Proc. of the 30th ESSCC, 2004, pp. 211--214.

Google Scholar

[5]

J. Chang et al., "The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series" JSSCC, April 2007.

Google Scholar

[6]

K. Mueller et al., "6T Cell circuit dependence GOX SBD Model for accurate prediction of observed Vccmin test voltage dependency", IEEE 42nd IRPS 2004.

Google Scholar

[7]

G. La Rosa et al., "Impact of NBTI Induced Statistical Variation to SRAM Cell Stability", 44^th IEEE IRPS 2006.

Google Scholar

[8]

S. Rauch, "Review and Reexamination of Reliability Effects Related to NBTI-Induced Statistical Variations", IEEE Trans. on Device and Material Reliability, Dec 2007.

Crossref

Google Scholar

[9]

R. Joshi et al., "Statistical Exploration of the Dual Supply Voltage Space of a 65nm PD/SOI CMOS SRAM Cell", IEEE ESSDIRC 2006, pp. 315--318.

Crossref

Google Scholar

[10]

R. Kanj et al., "Mixture Importance Sampling and its application to the analysis of SRAM designs in the presence of rare fail events", DAC 2006, pp. 69--72.

Digital Library

Google Scholar

[11]

W. Weibull, "A statistical distribution function of wide applicability" J. Appl. Mech.-Trans. ASME 18(3), 293--297, 1951.

Google Scholar

Cited By

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Lin YLi MGupta S(2024)Predictive Testing for Aging in SRAMs and Mitigation2024 IEEE International Test Conference (ITC)10.1109/ITC51657.2024.00050(293-302)Online publication date: 3-Nov-2024
https://doi.org/10.1109/ITC51657.2024.00050
Joshi RKanj RPelella Atuminaro AChan Y(2018)The Dawn of Predictive Chip Yield DesignIEEE Design & Test10.1109/MDT.2010.9527:6(36-45)Online publication date: 27-Dec-2018
https://dl.acm.org/doi/10.1109/MDT.2010.95
Jizhe Zhang Gupta S(2017)Wordline overdriving test: An effective predictive testing method for SRAMs against BTI aging2017 18th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2017.7918358(454-459)Online publication date: Mar-2017
https://doi.org/10.1109/ISQED.2017.7918358
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Index Terms

An elegant hardware-corroborated statistical repair and test methodology for conquering aging effects
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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Published In

ICCAD '09: Proceedings of the 2009 International Conference on Computer-Aided Design

November 2009

803 pages

ISBN:9781605588001

DOI:10.1145/1687399

General Chair:
Jaijeet Roychowdhury
Univ. of California, Berkeley, Berkeley, California

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 02 November 2009

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SIGDA

ICCAD '09: The International Conference on Computer-Aided Design

November 2 - 5, 2009

California, San Jose

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

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Lin YLi MGupta S(2024)Predictive Testing for Aging in SRAMs and Mitigation2024 IEEE International Test Conference (ITC)10.1109/ITC51657.2024.00050(293-302)Online publication date: 3-Nov-2024
https://doi.org/10.1109/ITC51657.2024.00050
Joshi RKanj RPelella Atuminaro AChan Y(2018)The Dawn of Predictive Chip Yield DesignIEEE Design & Test10.1109/MDT.2010.9527:6(36-45)Online publication date: 27-Dec-2018
https://dl.acm.org/doi/10.1109/MDT.2010.95
Jizhe Zhang Gupta S(2017)Wordline overdriving test: An effective predictive testing method for SRAMs against BTI aging2017 18th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2017.7918358(454-459)Online publication date: Mar-2017
https://doi.org/10.1109/ISQED.2017.7918358
Yao JYe ZWang Y(2015)An Efficient SRAM Yield Analysis and Optimization Method With Adaptive Online Surrogate ModelingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.233685123:7(1245-1253)Online publication date: Jul-2015
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Joshi RKanj R(2015)Designing stable circuits in the world of instability2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)10.1109/EDSSC.2015.7285101(265-268)Online publication date: Jun-2015
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Mitra SBose PCheng ECher CCho HJoshi RKim YLefurgy CLi YRodbell KSkadron KStathis JSzafaryn L(2014)The resilience wall: Cross-layer solution strategiesProceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)10.1109/VLSI-TSA.2014.6839639(1-11)Online publication date: Apr-2014
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Mitra SBose PCheng ECher CCho HJoshi RKim YLefurgy CLi YRodbell KSkadron KStathis JSzafaryn L(2014)The resilience wall: Cross-layer solution strategiesTechnical Papers of 2014 International Symposium on VLSI Design, Automation and Test10.1109/VLSI-DAT.2014.6834933(1-11)Online publication date: Apr-2014
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Han SKim BKim J(2013)Variation-Aware Aging Analysis in Digital ICsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.222888621:12(2214-2225)Online publication date: 1-Dec-2013
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Firouzi FKiamehr STahoori M(2013)Statistical analysis of BTI in the presence of process-induced voltage and temperature variations2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2013.6509663(594-600)Online publication date: Jan-2013
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Chen CAhmed FMilor L(2013)Impact of NBTI/PBTIon SRAMs within microprocessor systems: Modeling, simulation, and analysisMicroelectronics Reliability10.1016/j.microrel.2013.06.00353:9-11(1183-1188)Online publication date: Sep-2013
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