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Resynthesis of multi-phase pipelines

Authors:

Narendra V. Shenoy,

Robert K. Brayton,

Alberto L. Sangiovanni-VincentelliAuthors Info & Claims

DAC '93: Proceedings of the 30th international Design Automation Conference

Pages 490 - 496

https://doi.org/10.1145/157485.164995

Published: 01 July 1993 Publication History

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Cited By

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Sathyamurthy HSapatnekar SFishburn J(2006)Speeding up pipelined circuits through a combination of gate sizing and clock skew optimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.68126717:2(173-182)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.681267
Burks TSakallah KMudge T(1995)Critical paths in circuits with level-sensitive latchesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/92.3862273:2(273-291)Online publication date: 1-Jun-1995
https://dl.acm.org/doi/10.1109/92.386227
Soyata TFriedman E(1994)Synchronous performance and reliability improvement in pipelined ASICsProceedings Seventh Annual IEEE International ASIC Conference and Exhibit10.1109/ASIC.1994.404536(383-390)Online publication date: 1994
https://doi.org/10.1109/ASIC.1994.404536
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Resynthesis of multi-phase pipelines

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Sequential networks contain combinational logic blocks separated by registers. Application of combinational logic minimization techniques to the separate logic block results in improvement that is restricted by the placement of the registers; ...

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DAC '93: Proceedings of the 30th international Design Automation Conference

July 1993

768 pages

ISBN:0897915771

DOI:10.1145/157485

Chairman:
Alfred E. Dunlop
AT&T Bell Labs., Murray Hill, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 July 1993

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DAC93: The 30th ACM/IEEE Design Automation Conference

June 14 - 18, 1993

Texas, Dallas, USA

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Sathyamurthy HSapatnekar SFishburn J(2006)Speeding up pipelined circuits through a combination of gate sizing and clock skew optimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.68126717:2(173-182)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.681267
Burks TSakallah KMudge T(1995)Critical paths in circuits with level-sensitive latchesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/92.3862273:2(273-291)Online publication date: 1-Jun-1995
https://dl.acm.org/doi/10.1109/92.386227
Soyata TFriedman E(1994)Synchronous performance and reliability improvement in pipelined ASICsProceedings Seventh Annual IEEE International ASIC Conference and Exhibit10.1109/ASIC.1994.404536(383-390)Online publication date: 1994
https://doi.org/10.1109/ASIC.1994.404536
Shenoy NBrayton RSangiovanni-Vincentelli ALightner MJess J(1993)Minimum padding to satisfy short path constraintsProceedings of the 1993 IEEE/ACM international conference on Computer-aided design10.5555/259794.259821(156-161)Online publication date: 7-Nov-1993
https://dl.acm.org/doi/10.5555/259794.259821
Shenoy NBrayton RSangiovanni-Vincentelli A(1993)Minimum padding to satisfy short path constraintsProceedings of 1993 International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD.1993.580048(156-161)Online publication date: 1993
https://doi.org/10.1109/ICCAD.1993.580048

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High-performance dynamic elastic pipelines

Resynthesis and retiming for optimum partial scan

Retiming and resynthesis: optimizing sequential networks with combinational techniques

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High-performance dynamic elastic pipelines

Resynthesis and retiming for optimum partial scan

Retiming and resynthesis: optimizing sequential networks with combinational techniques

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