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Design for testability for path delay faults in sequential circuits

Authors:

Tapan J. Chakraborty,

Vishwani D. Agrawal,

Michael L. BushnellAuthors Info & Claims

DAC '93: Proceedings of the 30th international Design Automation Conference

Pages 453 - 457

https://doi.org/10.1145/157485.164973

Published: 01 July 1993 Publication History

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References

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T.J. Chakraborty, V.D. Agrawal, and M.L. Bushnell, "Path Delay Fault Simulation Algorithms for Sequential Circuits," Proc. Asian Test Syrup., pp. 52-56, November 1992.

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Cited By

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Yoshikawa Y(2013)A binding algorithm in high-level synthesis for path delay testability2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2013.6509653(546-551)Online publication date: Jan-2013
https://doi.org/10.1109/ASPDAC.2013.6509653
Chakradhar SIyer MAgrawal V(2006)Energy models for delay testingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.38773314:6(728-739)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.387733
Ke WMenon P(2006)Path-delay-fault testable nonscan sequential circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.38441914:5(576-582)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.384419
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Index Terms

Design for testability for path delay faults in sequential circuits
1. Hardware
  1. Hardware test
    1. Design for testability
    2. Test-pattern generation and fault simulation
  2. Integrated circuits
    1. Logic circuits
      1. Sequential circuits

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DAC '93: Proceedings of the 30th international Design Automation Conference

July 1993

768 pages

ISBN:0897915771

DOI:10.1145/157485

Chairman:
Alfred E. Dunlop
AT&T Bell Labs., Murray Hill, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 July 1993

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DAC93: The 30th ACM/IEEE Design Automation Conference

June 14 - 18, 1993

Texas, Dallas, USA

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Yoshikawa Y(2013)A binding algorithm in high-level synthesis for path delay testability2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2013.6509653(546-551)Online publication date: Jan-2013
https://doi.org/10.1109/ASPDAC.2013.6509653
Chakradhar SIyer MAgrawal V(2006)Energy models for delay testingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.38773314:6(728-739)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.387733
Ke WMenon P(2006)Path-delay-fault testable nonscan sequential circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.38441914:5(576-582)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.384419
Vorisek VKoch TFischer H(2004)At-Speed Testing of SOC ICsProceedings of the conference on Design, automation and test in Europe - Volume 310.5555/968880.969237Online publication date: 16-Feb-2004
https://dl.acm.org/doi/10.5555/968880.969237
Maruyama DKanuma AMochiyama TKomatsu HSugiyama YIto N(2004)Detection of multiple transitions in delay fault test of SPARC64 microprocessorProceedings of the 2004 IEEE/ACM International conference on Computer-aided design10.1109/ICCAD.2004.1382701(893-898)Online publication date: 7-Nov-2004
https://dl.acm.org/doi/10.1109/ICCAD.2004.1382701
Iwagaki Ohtake Fujiwara (2003)Reducibility of sequential test generation to combinational test generation for several delay fault modelsProceedings of the 7th International Conference on Properties and Applications of Dielectric Materials (Cat No 03CH37417) ATS-0310.1109/ATS.2003.1250783(58-63)Online publication date: 2003
https://doi.org/10.1109/ATS.2003.1250783
Ohtake SMiwa SFujiwara H(2002)A method of test generation for path delay faults in balanced sequential circuitsProceedings 20th IEEE VLSI Test Symposium (VTS 2002)10.1109/VTS.2002.1011160(321-327)Online publication date: 2002
https://doi.org/10.1109/VTS.2002.1011160
Chakraborty TAgrawal VBushnell M(2000)Improving path delay testability of sequential circuitsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/92.9022688:6(736-741)Online publication date: 1-Dec-2000
https://dl.acm.org/doi/10.1109/92.902268
Mukherjee NChakraborty TBhawmik S(1998)A BIST scheme for the detection of path-delay faultsProceedings of the 1998 IEEE International Test Conference10.5555/648020.745938Online publication date: 18-Oct-1998
https://dl.acm.org/doi/10.5555/648020.745938
Parthasarathy GBushnell M(1998)Towards simultaneous delay-fault built-in self-test and partial-scan insertionProceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)10.1109/VTEST.1998.670870(210-217)Online publication date: 1998
https://doi.org/10.1109/VTEST.1998.670870
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Improving path delay testability of sequential circuits

Delay Fault Testability on Two-Rail Logic Circuits

On Redundant Path Delay Faults in Synchronous Sequential Circuits

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Improving path delay testability of sequential circuits

Delay Fault Testability on Two-Rail Logic Circuits

On Redundant Path Delay Faults in Synchronous Sequential Circuits

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