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High-level synthesis of fault-secure microarchitectures

Authors:

Ramesh Karri,

Alex OrailoğluAuthors Info & Claims

DAC '93: Proceedings of the 30th international Design Automation Conference

Pages 429 - 433

https://doi.org/10.1145/157485.164963

Published: 01 July 1993 Publication History

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Campbell KLin DHe LYang LGurumani SRupnow KMitra SChen D(2019)Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level SynthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.283710338:7(1345-1358)Online publication date: Jul-2019
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High-level synthesis of fault-secure microarchitectures
1. Hardware

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DAC '93: Proceedings of the 30th international Design Automation Conference

July 1993

768 pages

ISBN:0897915771

DOI:10.1145/157485

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Alfred E. Dunlop
AT&T Bell Labs., Murray Hill, NJ

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Published: 01 July 1993

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https://doi.org/10.1109/TCAD.2018.2837103
Campbell KLin DMitra SChen D(2015)Hybrid quick error detection (H-QED)Proceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2753768(1-6)Online publication date: 7-Jun-2015
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Liu YWu K(2014)Fault-Duration And-Location Aware CED Technique With Runtime AdaptabilityIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.225148422:3(507-515)Online publication date: 1-Mar-2014
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Interconnect oriented microarchitectures and resource binding in behavioral synthesis

High-Level Test Synthesis: A Survey from Synthesis Process Flow Perspective

Layout-driven RTL binding techniques for high-level synthesis

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