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Partial scan with retiming

Authors:

Dimitrios Kagaris,

Spyros TragoudasAuthors Info & Claims

DAC '93: Proceedings of the 30th international Design Automation Conference

Pages 249 - 254

https://doi.org/10.1145/157485.164881

Published: 01 July 1993 Publication History

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Cited By

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Peichen Pan (2006)Partial Scan with Pre-selected Scan Signals32nd Design Automation Conference10.1109/DAC.1995.250088(189-194)Online publication date: Dec-2006
https://doi.org/10.1109/DAC.1995.250088
Chakradhar SDey S(2006)Resynthesis and retiming for optimum partial scanIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.75907818:5(621-630)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.759078
Stroele AWunderlich H(2006)Hardware-optimal test register insertionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.70383317:6(531-539)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.703833
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Index Terms

Partial scan with retiming
1. Hardware
2. Mathematics of computing
  1. Discrete mathematics
    1. Graph theory
      1. Paths and connectivity problems

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Published In

DAC '93: Proceedings of the 30th international Design Automation Conference

July 1993

768 pages

ISBN:0897915771

DOI:10.1145/157485

Chairman:
Alfred E. Dunlop
AT&T Bell Labs., Murray Hill, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 July 1993

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DAC93: The 30th ACM/IEEE Design Automation Conference

June 14 - 18, 1993

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Peichen Pan (2006)Partial Scan with Pre-selected Scan Signals32nd Design Automation Conference10.1109/DAC.1995.250088(189-194)Online publication date: Dec-2006
https://doi.org/10.1109/DAC.1995.250088
Chakradhar SDey S(2006)Resynthesis and retiming for optimum partial scanIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.75907818:5(621-630)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.759078
Stroele AWunderlich H(2006)Hardware-optimal test register insertionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.70383317:6(531-539)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.703833
El-Maleh AMarchok TRajski JMaly W(2006)Behavior and testability preservation under the retiming transformationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.63121716:5(528-543)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.631217
Kagaris DTragoudas SBhatia D(2006)Pseudo-exhaustive built-in TPG for sequential circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.40671814:9(1160-1171)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.406718
Fujiwara H(2000)A New Class of Sequential Circuits with Combinational Test Generation ComplexityIEEE Transactions on Computers10.1109/12.86932149:9(895-905)Online publication date: 1-Sep-2000
https://dl.acm.org/doi/10.1109/12.869321
Pan PLiu C(1999)Partial Scan with Preselected Scan SignalsIEEE Transactions on Computers10.1109/12.79522848:9(1000-1005)Online publication date: 1-Sep-1999
https://dl.acm.org/doi/10.1109/12.795228
Chen CHwang T(1998)Layout Driven Selection and Chaining of Partial Scan Flip-FlopsJournal of Electronic Testing: Theory and Applications10.1023/A:100838101552713:1(19-27)Online publication date: 1-Aug-1998
https://dl.acm.org/doi/10.1023/A%3A1008381015527
Yotsuyanagi HKajihara SKinoshita K(1997)Synthesis of Sequential Circuits by Redundancy Removal and RetimingJournal of Electronic Testing: Theory and Applications10.1023/A:100825190195911:1(81-92)Online publication date: 1-Aug-1997
https://dl.acm.org/doi/10.1023/A%3A1008251901959
Balakrishnan AChakradhar S(1996)Retiming with logic duplication transformationProceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication10.5555/525699.834783Online publication date: 3-Jan-1996
https://dl.acm.org/doi/10.5555/525699.834783
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Model Predictive Control for Partial Differential Equations

Retiming-Based Partial Scan

Iterational retiming: maximize iteration-level parallelism for nested loops

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Model Predictive Control for Partial Differential Equations

Retiming-Based Partial Scan

Iterational retiming: maximize iteration-level parallelism for nested loops

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