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Register traffic analysis for streamlining inter-operation communication in fine-grain parallel processors

Authors:

Manoj Franklin,

Gurindar S. SohiAuthors Info & Claims

ACM SIGMICRO Newsletter, Volume 23, Issue 1-2

Pages 236 - 245

https://doi.org/10.1145/144965.145818

Published: 10 December 1992 Publication History

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Fadishei HDeldari HNaghibzadeh M(2014)Pre-execution power consumption prediction of computational multithreaded workloadsCluster Computing10.1007/s10586-014-0401-017:4(1323-1333)Online publication date: 1-Dec-2014
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Goswami NCao BLi T(2013)Power-performance co-optimization of throughput core architecture using resistive memoryProceedings of the 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2013.6522331(342-353)Online publication date: 23-Feb-2013
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Sohi GVijaykumar T(2009)Speculatively Multithreaded ArchitecturesMulticore Processors and Systems10.1007/978-1-4419-0263-4_4(111-143)Online publication date: 3-Aug-2009
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Index Terms

Register traffic analysis for streamlining inter-operation communication in fine-grain parallel processors
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
2. Hardware

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Information

Published In

ACM SIGMICRO Newsletter Volume 23, Issue 1-2

Dec. 1992

300 pages

ISSN:1050-916X

DOI:10.1145/144965

Editor:
Wen-mei Hwu

Issue’s Table of Contents

MICRO 25: Proceedings of the 25th annual international symposium on Microarchitecture
December 1992
301 pages
ISBN:0818631759
Chairman:
Wen-mei Hwu

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 10 December 1992

Published in SIGMICRO Volume 23, Issue 1-2

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Fadishei HDeldari HNaghibzadeh M(2014)Pre-execution power consumption prediction of computational multithreaded workloadsCluster Computing10.1007/s10586-014-0401-017:4(1323-1333)Online publication date: 1-Dec-2014
https://dl.acm.org/doi/10.1007/s10586-014-0401-0
Goswami NCao BLi T(2013)Power-performance co-optimization of throughput core architecture using resistive memoryProceedings of the 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2013.6522331(342-353)Online publication date: 23-Feb-2013
https://dl.acm.org/doi/10.1109/HPCA.2013.6522331
Sohi GVijaykumar T(2009)Speculatively Multithreaded ArchitecturesMulticore Processors and Systems10.1007/978-1-4419-0263-4_4(111-143)Online publication date: 3-Aug-2009
https://doi.org/10.1007/978-1-4419-0263-4_4
Lee KGrosspietsch KChan Y(2003)An Alternative Superscalar Architecture with Integer Execution Units OnlyAdvanced Parallel Processing Technologies10.1007/978-3-540-39425-9_7(57-65)Online publication date: 2003
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Uht AKhalafi AMorano Dde Alba MKaeli D(2002)Realizing High IPC Using Time-Tagged Resource-Flow ComputingEuro-Par 2002 Parallel Processing10.1007/3-540-45706-2_67(490-499)Online publication date: 20-Aug-2002
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Zhou SWang HTong D(2021)Prediction of Register Instance Usage and Time-sharing Register for Extended Register Reuse SchemeProceedings of the 26th Asia and South Pacific Design Automation Conference10.1145/3394885.3431412(216-221)Online publication date: 18-Jan-2021
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Jacob B(2016)The Case for VLIW-CMP as a Building Block for ExascaleIEEE Computer Architecture Letters10.1109/LCA.2015.242469915:1(54-57)Online publication date: 1-Jan-2016
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Van Craeynest KJaleel AEeckhout LNarvaez PEmer JLu STorrellas J(2012)Scheduling heterogeneous multi-cores through Performance Impact Estimation (PIE)Proceedings of the 39th Annual International Symposium on Computer Architecture10.5555/2337159.2337184(213-224)Online publication date: 9-Jun-2012
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Van Craeynest KJaleel AEeckhout LNarvaez PEmer J(2012)Scheduling heterogeneous multi-cores through Performance Impact Estimation (PIE)ACM SIGARCH Computer Architecture News10.1145/2366231.233718440:3(213-224)Online publication date: 9-Jun-2012
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Gebhart MJohnson DTarjan DKeckler SDally WLindholm ESkadron K(2012)A Hierarchical Thread Scheduler and Register File for Energy-Efficient Throughput ProcessorsACM Transactions on Computer Systems10.1145/2166879.216688230:2(1-38)Online publication date: 1-Apr-2012
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