article

Free access

Exploiting instruction-level parallelism with the conjugate register file scheme

Authors:

Meng-chou Chang,

Feipei Lai,

Rung-ji ShangAuthors Info & Claims

ACM SIGMICRO Newsletter, Volume 23, Issue 1-2

Pages 29 - 32

https://doi.org/10.1145/144965.144986

Published: 10 December 1992 Publication History

PDF eReader

References

[1]

G. 3. Cha/tin, "Register Allocation and Spilling Via Graph Coloring," Proceedings of tAe SIGPLAN '8~ $Timposium on Compiler Construction, SIGPLAN Notices, Vol. 17, no. 6 (June 1982), pp. 98-105.

Digital Library

Google Scholar

[2]

M. D. Smith, M. S. Lain, and M. A. Horowitz, "Boosting Beyond Static Scheduling in a Superscalar Processor," Proceedings of the 17th Annual International Symposium on Computer Architecittre (May 1990), pp. 344-354.

Digital Library

Google Scholar

Cited By

View all

Feipei Lai Chia-Jung Hsieh (1994)Reducing procedure call overhead: optimizing register usage at procedure callsProceedings of 1994 International Conference on Parallel and Distributed Systems10.1109/ICPADS.1994.590416(649-654)Online publication date: 1994
https://doi.org/10.1109/ICPADS.1994.590416
Feipei Lai Yung-Kuang Chao (1994)The complementary relationship of interprocedural register allocation and inliningProceedings of 1994 IEEE International Conference on Computer Languages (ICCL'94)10.1109/ICCL.1994.288375(253-264)Online publication date: 1994
https://doi.org/10.1109/ICCL.1994.288375
Yamana HSato MKodama YSakane HSakai SYamaguchi YValero M(1995)A macrotask-level unlimited speculative execution on multiprocessorsProceedings of the 9th international conference on Supercomputing10.1145/224538.224620(328-337)Online publication date: 3-Jul-1995
https://dl.acm.org/doi/10.1145/224538.224620

Recommendations

Efficient Exploitation of Instruction-Level Parallelism for Superscalar Processors by the Conjugate Register File Scheme

This paper introduces a novel superscalar micro-architecture, called IAS-S, and its related software techniques. We treat two basic problems in superscalar machines. First, we seek a feasible hardware platform which allows the compiler to perform more ...
Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading

To achieve high performance, contemporary computer systems rely on two forms of parallelism: instruction-level parallelism (ILP) and thread-level parallelism (TLP). Wide-issue super-scalar processors exploit ILP by executing multiple instructions from a ...
Exploiting Java instruction/thread level parallelism with horizontal multithreading

Java bytecodes can be executed with the following three methods: a Java interpretor running on a particular machine interprets bytecodes; a Just-In-Time (JIT) compiler translates bytecodes to the native primitives of the particular machine and the ...

Comments

Information & Contributors

Information

Published In

ACM SIGMICRO Newsletter Volume 23, Issue 1-2

Dec. 1992

300 pages

ISSN:1050-916X

DOI:10.1145/144965

Editor:
Wen-mei Hwu

Issue’s Table of Contents

MICRO 25: Proceedings of the 25th annual international symposium on Microarchitecture
December 1992
301 pages
ISBN:0818631759
Chairman:
Wen-mei Hwu

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 10 December 1992

Published in SIGMICRO Volume 23, Issue 1-2

Check for updates

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

3
Total Citations
View Citations
718
Total Downloads

Downloads (Last 12 months)42
Downloads (Last 6 weeks)6

Reflects downloads up to 27 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Feipei Lai Chia-Jung Hsieh (1994)Reducing procedure call overhead: optimizing register usage at procedure callsProceedings of 1994 International Conference on Parallel and Distributed Systems10.1109/ICPADS.1994.590416(649-654)Online publication date: 1994
https://doi.org/10.1109/ICPADS.1994.590416
Feipei Lai Yung-Kuang Chao (1994)The complementary relationship of interprocedural register allocation and inliningProceedings of 1994 IEEE International Conference on Computer Languages (ICCL'94)10.1109/ICCL.1994.288375(253-264)Online publication date: 1994
https://doi.org/10.1109/ICCL.1994.288375
Yamana HSato MKodama YSakane HSakai SYamaguchi YValero M(1995)A macrotask-level unlimited speculative execution on multiprocessorsProceedings of the 9th international conference on Supercomputing10.1145/224538.224620(328-337)Online publication date: 3-Jul-1995
https://dl.acm.org/doi/10.1145/224538.224620

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Efficient Exploitation of Instruction-Level Parallelism for Superscalar Processors by the Conjugate Register File Scheme

Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading

Exploiting Java instruction/thread level parallelism with horizontal multithreading