Article

Free access

A performance evaluation of optimal hybrid cache coherency protocols

Authors:

ASPLOS V: Proceedings of the fifth international conference on Architectural support for programming languages and operating systems

Pages 149 - 160

https://doi.org/10.1145/143365.143503

Published: 01 September 1992 Publication History

PDF eReader

References

[1]

M. Accetta, R. Baron, W. Bolosky, D. Golub, R. Rashid, A. Tevanian, and M. Young. Mach: A new kernel foundation for UNIX development. In Proe. o/ the Summer 1986 USENIX Technical Conference and Exhibition, Pittsburgh, PA, June 1986.

Google Scholar

[2]

A. Agarwal, R. Simoni, J. Hennessy, and M. Horowitz. An evaluation of directory schemes for cache coherence. In Proceedings o/the 15th Annual International Symposium on Computer Architecture, pages 280-289, June 1988.

Digital Library

Google Scholar

[3]

James Archibald and Jeaat~Loup Baer. Cache coherence protocols: Evaluation using a multiprocessor simulation model. A CM Transactions on Computer Systems, 4(4):273-298, November 1986.

Digital Library

Google Scholar

[4]

H. B. Bakogh, G. F. Grohoski, and R. K. Montoye. The IBM RISC System/6000 processor: Hardware overview. IBM Journal of Research and Development, 36(1):12-22, 1990.

Digital Library

Google Scholar

[5]

John K. Bennett, John B. Carter, and Willy Zwaenepoel. Adaptive software cache management for distributed shared memory architectures. In Proceedings o/the 17th Annual International Symposium on Computer Architecture, pages 125-135, June 1990.

Digital Library

Google Scholar

[6]

John K. Bennett, John B. Carter, and Willy Zwaenepoel. Munin: Distributed shared memory based on type-specific memory coherence, in Proceedings o/ the Second PPoPP, pages 168-176, March 1990. ACM SIGPLAN Notices 25:3.

Digital Library

Google Scholar

[7]

B. N. Bershad, E. D. Lazowska, and H. M. Levy. Presto: A system for object-oriented parallel programming. Software- Practice and Experience, 18(8):713- 732, 1988.

Digital Library

Google Scholar

[8]

W. J. Bolosky and M. L. Scott. A Trace-Based Comparison of Shared Memory Multiprocessors using Optimal Off-Line Analysis. Technical report, U. of Rochester CSD, December 1991.

Digital Library

Google Scholar

[9]

William J. Bolosky, Michael L. Scott, Robert P. Fitzgerald, Robert J. Fowler, and Alan L. Cox. NUMA policies and their relation to memory architecture. In Proceedings o/the Fourth International Conference on Architectural Support/or Programming Languages and Operating Systems, pages 212 - 221, 1991.

Digital Library

Google Scholar

[10]

James Boyle, Ralph Butler, Terrence Disz, Barnett Blickfeld, Ewing Lusk, and Ross Overbeek. Portable Programs/or Parallel Processors. Holt, Rinehart and Winston, 1987.

Digital Library

Google Scholar

[11]

Lucien M. Censier and Paul Feautrier. A new solution to coherence problems in muRicache systems. IEEE Transactions on Computers, C-27(12):1112-1118, December 1978.

Digital Library

Google Scholar

[12]

David R. Cheriton, Hendrik A. Goosen, and Philip Ms~ chanick. Restructuring a para}lel simulation to improve cache behavior in a shaxed-memory multiprocessor: A first experience. In Proceedings of the international Symposium on Shared-Memory Multiprocessing, pages 109-118, 1991.

Google Scholar

[13]

Eric Cooper and Richard Draves. C Threads. Technical report, Carnegie-Mellon University, Computer Science Department, nov 1990.

Google Scholar

[14]

Corollary, Inc. C-bus H Specification, Revision 1.0. Corollary, Inc., 2802 Kelvin Avenue, Irvine, California 92714, 1991.

Google Scholar

[15]

Alan L. Cox. The Implementation and Evaluation o/a Coherent Memory Abstraction/or NUMA Multiproces. sops. PhD thesis, University of Rochester, Department of Computer Science, may 1992.

Digital Library

Google Scholar

[16]

Alan L. Cox and Robert J. Fowler. The implementation of a coherent memory abstraction on a NUMA multiprocessor: Experiences with PLATINUM. In Proceedings o/the 12th A CM Symposium on Operating System Principles, pages 32-44, Litchfield Park, AZ, December 1989.

Digital Library

Google Scholar

[17]

W. P. Crowley, C. P. Hendrickson, and T. E. Rudy. The SIMPLE code. Technical report, Lawrence Livermore Laboratory, 1978. UCID-17715.

Google Scholar

[18]

Czarek Dubnicki and Thomas J. LeBlanc. Adjustable block size coherent caches. In Proceedings o/the 19th Annual International Symposium on Computer Archi. tecture, pages 170-180, 1992.

Digital Library

Google Scholar

[19]

S. J. Eggers and T. E. Jeremiassen. Eliminating False Sharing. In Prec. 199I Intl. Conf. on Parallel Processing, pages 377-381, 1991. Volume I.

Google Scholar

[20]

Susan J. Eggers and Randy H. Katz. A characterization of sharing in parallel programs and its application to coherency protocol evaluation. In Proceedings of the lath International Symposium on Computer Architecture, pages 373-382, 1988.

Digital Library

Google Scholar

[21]

Susan j. Eggers and Randy H. Katz. Evaluating the performance of four snooping cache coherency protocols. Technical Report UCB/CSD 88/478, Computer Science Division (EECS), University of California, Berkeley, December 1988.

Digital Library

Google Scholar

[22]

Susan J. Eggers and Randy H. Katz. The effect of sharing on the cache and bus performance of parallel programs. In Proceedings o/the Third international Conference on Arehicteetural Support for Program. ruing Languages and Operating Systems (ASPLOS- llI), pages 257-270, April 1989.

Digital Library

Google Scholar

[23]

A. Garcia, D. Foster, and R. Freitas. The Advanced Computing Environment Multiprocessor Workstation. Research Report RC-14419, IBM T.J. Watson Research Center, March 1989.

Google Scholar

[24]

Armando Gaxda. Efficient Rendering of Synthetic In. ages. PhD thesis, Massachusetts Institute of Technology, February 1988.

Google Scholar

[25]

Aaron Goldberg and John itennessy. Mtooh A method for isolating memory bottlenecks in shared memory multiprocessor programs. In Proceedings of the 1991 Conference on Parallel Processing, pages II-251-II- 257, 1991.

Google Scholar

[26]

J. R. Goodman, M. K. Vernon, and P. J. Woest. Efficient Synchronization Primitives for Large-Scale Cache-Coherent Multiprocessors. In Proceedings of the Third International Conference on Architectural Support for Programming Languages and Operating Systems, pages 64-75, April 1989.

Digital Library

Google Scholar

[27]

James R. Goodman. Using cache memory to reduce processor-memory traffic. In Proceedings of the l Oth International Symposium on Computer Architecture, pages 124-131, 1983.

Digital Library

Google Scholar

[28]

Norman P. Jouppi. Improving direct-mapped cache performance by the addition of a small fully, associative cache and prefetch buffers. In Proceedings of the 17th Annual International Symposium on Computer Architecture, pages 364-373, 1990.

Digital Library

Google Scholar

[29]

A. R. Karlin, M. S. Manasse, L. Rudolph, and D. D. Sleator. Competitive snoopy caching. Algorithmica, pages 79-119, March 1988.

Digital Library

Google Scholar

[30]

R. H. Katz, S. J. Eggers, D. A. Wood, C. L. PerMns, and R. G. Sheldon. Implementing a cache consistency protocol. In Proceedings of the l~th International Symposium on Computer Architecture, pages 276-283, 1985.

Digital Library

Google Scholar

[31]

Daniel Lenoski, James Landon, Kourosh Gharachor- 1oo, Anoop Gupta, and John Hennessy. The directorybased cache coherence protocol for the DASH mulfiprocessor. In Proceedings o/the 17th Annual International Symposium on Computer Architecture, pages 148-159, June 1990.

Digital Library

Google Scholar

[32]

John M. Mellor-Crummey and Michael L. Scott. Synchronization without contention. In Proceedings o/the Fourth International Conference on Architectural Support/or Programming Languages and Operating Systems, pages 269-278, April 1991.

Digital Library

Google Scholar

[33]

MIPS Computer Systems, Inc. MIPS R~O00 Microprocessor User's Manual. Integrated Device Technology, Inc., 1991.

Google Scholar

[34]

James M. Ortega and Robert O. Voigt. Solution of Partial Differential Equations on Vector an d Parallel Computers. SIAM Review, 27(2):149-240, June 1985.

Crossref

Google Scholar

[35]

J. P. Singh, W.-D. Weber, and A. Gnpta. SPLASH: Stanford Parallel Applications for Shared-Memory. Available by anonymous FTP, April 1991.

Google Scholar

[36]

J. Stone and A. Norton. The VM/EPEX FORTRAN Preprocessor Reference. IBM, 1985. Research Report RGll408.

Google Scholar

[37]

Charles P. Thacker and Lawrence C. Stewart. Firefly: a Multiprocessor Workstation. In Proceedings of the Second International Conference on Architectural Support/or Programming Languages and Operating Systems, pages 164-172, PaJo Alto, CA, October 1987. Oper. Sys. Review v21(4), 10/87.

Crossref

Google Scholar

[38]

Josep Torrellas, Monies S. Lam, and John L. ttennessy. Shared data placement optimizations to reduce multiprocessor cache miss rates. In International Conference on Parallel Processing, pages 11-266 - I1-270. The Pennsylvania State University Press, 1990.

Google Scholar

Cited By

View all

Altwaijry HAlzahrani D(2013)Improved-MOESI Cache Coherence ProtocolArabian Journal for Science and Engineering10.1007/s13369-013-0787-739:4(2739-2748)Online publication date: 12-Sep-2013
https://doi.org/10.1007/s13369-013-0787-7
Nanri TSato HShimasaki M(2005)Cost estimation of coherence protocols of software managed cache on distributed shared memory systemHigh Performance Computing10.1007/BFb0024228(335-342)Online publication date: 9-Jun-2005
https://doi.org/10.1007/BFb0024228
Giorgi RPrete C(1999)PSCRIEEE Transactions on Parallel and Distributed Systems10.1109/71.78086810:7(742-763)Online publication date: 1-Jul-1999
https://dl.acm.org/doi/10.1109/71.780868
Show More Cited By

Index Terms

A performance evaluation of optimal hybrid cache coherency protocols

Recommendations

Evaluating the performance of four snooping cache coherency protocols
ISCA '89: Proceedings of the 16th annual international symposium on Computer architecture

Write-invalidate and write-broadcast coherency protocols have been criticized for being unable to achieve good bus performance across all cache configurations. In particular, write-invalidate performance can suffer as block size increases; and large ...
A Performance Evaluation of Optimal Hybrid Cache Coherency Protocols
Evaluating the performance of four snooping cache coherency protocols
Special Issue: Proceedings of the 16th annual international symposium on Computer Architecture

Write-invalidate and write-broadcast coherency protocols have been criticized for being unable to achieve good bus performance across all cache configurations. In particular, write-invalidate performance can suffer as block size increases; and large ...

Comments

Information & Contributors

Information

Published In

ASPLOS V: Proceedings of the fifth international conference on Architectural support for programming languages and operating systems

September 1992

308 pages

ISBN:0897915348

DOI:10.1145/143365

Chairman:
Barry Flahive
Hewlett-Packard
,
Editor:
Richard L. Wexelblat

ACM SIGPLAN Notices Volume 27, Issue 9
Sept. 1992
278 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/143371
Editors:
Richard L. Wexelblat,
Barry Flahive
Hewlett-Packard
Issue’s Table of Contents

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 September 1992

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

ASPLOS92

Sponsor:

ASPLOS92: 5th Conference on Architectural Support of Programming Languages & Operating Systems

October 12 - 15, 1992

Massachusetts, Boston, USA

Acceptance Rates

Overall Acceptance Rate 535 of 2,713 submissions, 20%

Upcoming Conference

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

13
Total Citations
View Citations
601
Total Downloads

Downloads (Last 12 months)103
Downloads (Last 6 weeks)9

Reflects downloads up to 04 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Altwaijry HAlzahrani D(2013)Improved-MOESI Cache Coherence ProtocolArabian Journal for Science and Engineering10.1007/s13369-013-0787-739:4(2739-2748)Online publication date: 12-Sep-2013
https://doi.org/10.1007/s13369-013-0787-7
Nanri TSato HShimasaki M(2005)Cost estimation of coherence protocols of software managed cache on distributed shared memory systemHigh Performance Computing10.1007/BFb0024228(335-342)Online publication date: 9-Jun-2005
https://doi.org/10.1007/BFb0024228
Giorgi RPrete C(1999)PSCRIEEE Transactions on Parallel and Distributed Systems10.1109/71.78086810:7(742-763)Online publication date: 1-Jul-1999
https://dl.acm.org/doi/10.1109/71.780868
Bianchini RCarrera EKontothanassis L(1998)Evaluating the Effect of Coherence Protocols on the Performance of Parallel Programming ConstructsInternational Journal of Parallel Programming10.1023/A:101874491948326:2(143-181)Online publication date: 1-Apr-1998
https://dl.acm.org/doi/10.1023/A%3A1018744919483
Bianchini RCarrera EKontothanassis L(1997)The interaction of parallel programming constructs and coherence protocolsACM SIGPLAN Notices10.1145/263767.26377432:7(69-79)Online publication date: 21-Jun-1997
https://dl.acm.org/doi/10.1145/263767.263774
Bianchini RCarrera EKontothanassis LSchreiber RPingali K(1997)The interaction of parallel programming constructs and coherence protocolsProceedings of the sixth ACM SIGPLAN symposium on Principles and practice of parallel programming10.1145/263764.263774(69-79)Online publication date: 21-Jun-1997
https://dl.acm.org/doi/10.1145/263764.263774
Srbljic SVranesic ZStumm MBudin L(1997)Analytical Prediction of Performance for Cache Coherence ProtocolsIEEE Transactions on Computers10.1109/12.64429146:11(1155-1173)Online publication date: 1-Nov-1997
https://dl.acm.org/doi/10.1109/12.644291
Bianchini RLeBlanc TVeenstra J(1996)Categorizing Network Traffic in Update-Based Protocols on Scalable MultiprocessorsProceedings of the 10th International Parallel Processing Symposium10.5555/645606.661194(142-151)Online publication date: 15-Apr-1996
https://dl.acm.org/doi/10.5555/645606.661194
Kim JVaidya NYew P(1996)A cost-comparison approach for adaptive distributed shared memoryProceedings of the 10th international conference on Supercomputing10.1145/237578.237584(44-51)Online publication date: 1-Jan-1996
https://dl.acm.org/doi/10.1145/237578.237584
Bianchini RLeBlanc TVeenstra J(1996)Categorizing network traffic in update-based protocols on scalable multiprocessorsProceedings of International Conference on Parallel Processing10.1109/IPPS.1996.508050(142-151)Online publication date: 1996
https://doi.org/10.1109/IPPS.1996.508050
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Evaluating the performance of four snooping cache coherency protocols

A Performance Evaluation of Optimal Hybrid Cache Coherency Protocols

Evaluating the performance of four snooping cache coherency protocols