research-article

System-level throughput analysis for process variation aware multiple voltage-frequency island designs

Authors:

Siddharth Garg,

Diana MarculescuAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 13, Issue 4

Article No.: 59, Pages 1 - 25

https://doi.org/10.1145/1391962.1391967

Published: 03 October 2008 Publication History

Abstract

The increasing variability in manufacturing process parameters is expected to lead to significant performance degradation in deep submicron technologies. Multiple Voltage-Frequency Island (VFI) design styles with fine-grained, process-variation aware clocking have recently been shown to possess increased immunity to manufacturing process variations. In this article, we propose a theoretical framework that allows designers to quantify the performance improvement that is to be expected if they were to migrate from a fully synchronous design to the proposed multiple VFI design style. Specifically, we provide techniques to efficiently and accurately estimate the probability distribution of the execution rate (or throughput) of both single and multiple VFI systems under the influence of manufacturing process variations. Finally, using an MPEG-2 encoder benchmark, we demonstrate how the proposed analysis framework can be used by designers to make architectural decisions such as the granularity of VFI domain partitioning based on the throughput constraints their systems are required to satisfy.

References

[1]

Belete, D., Razdan, A., Schwarz, W., Raina, R., Hawkins, C., and Morehead, J. 2002. Use of DFT techniques in speed grading a 1 GHz+ microprocessor. In Proceedings of the International Test Conference. 1111--1119.

Digital Library

[2]

Bowman, K., Duvall, S., and Meindl, J. 2002. Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration. IEEE J. Solid-State Circ. 37, 2.

[3]

Carloni, L. and Sangiovanni-Vincentelli, A. 2000. Performance analysis and optimization of latency insensitive systems. In Proceedings of the 37th Conference on Design Automation. 361--367.

Digital Library

[4]

Chang, H. and Sapatnekar, S. 2003. Statistical timing analysis considering spatial correlations using a single pert-Like traversal. In Proceedings of the International Conference on Computer-Aided Design (ICCAD). 621--625.

Digital Library

[5]

Chapiro, D. 1984. Globally-asynchronous locally-synchronous systems. Ph.D. thesis, Stanford University.

Digital Library

[6]

Chelcea, T. and Nowick, S. 2001. Robust interfaces for mixed-timing systems with application to latency-insensitive protocols. In Proceedings of the 38th Conference on Design Automation. 21--26.

Digital Library

[7]

Datta, A., Bhunia, S., Banerjee, N., and Roy, K. 2005. A power-aware GALS architecture for real-time algorithm-specific tasks. In Proceedings of the 6th International Symposium on Quality of Electronic Design. 358--363.

Digital Library

[8]

de Veciana, G. and Jacome, M. 1998. Hierarchical algorithms for assessing probabilistic constraints on system performance. In Proceedings of the IEEE/ACM Design Automation Conference (DAC).

Digital Library

[9]

Devgan, A. and Kashyap, C. 2003. Block-based static timing analysis with uncertainty. In Proceedings of the International Conference on Computer-Aided Design (ICCAD). 607--614.

Digital Library

[10]

Ernst, D., Flautner, K., Mudge, T., Kim, N., Das, S., Pant, S., Rao, R., Pham, T., Ziesler, C., Blaauw, D., et al. 2003. Razor: A low-power pipeline based on circuit-level timing speculation. In Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture, 7--18.

Digital Library

[11]

Friedberg, P., Cheung, W., and Spanos, C. 2006. Spatial modeling of micron-scale gate length variation. In Data Analysis and Modeling for Patterning Control III. SPIE, vol. 6155.

[12]

Hemani, A., Meincke, T., Kumar, S., Postula, A., Olsson, T., Nilsson, P., Oberg, J., Ellervee, P., and Lundqvist, D. 1999. Lowering power consumption in clock by using globally asynchronous locally synchronous design style. In Proceedings of the 36th ACM/IEEE Conference on Design Automation Conference, 873--878.

Digital Library

[13]

Hu, X. S., Zhou, T., and Sha, E. H.-M. 2001. Estimating probabilistic timing performance for real-time embedded systems. IEEE Trans. TVLSI.

Digital Library

[14]

Hung, W.-L., Wu, X., and Xie, Y. 2006. Guaranteeing performance yield in high-level synthesis. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. 303--309.

Digital Library

[15]

Karp, R. 1978. A characterization of the minimum cycle mean in a digraph. Discrete Math 23.

[16]

Kulkarni, S., Sylvester, D., and Blaauw, D. 2006. A statistical framework for post-silicon tuning through body bias clustering. Proceedings of the International Conference on Computer-Aided Design (ICCAD). 39--46.

Digital Library

[17]

Lackey, D., Zuchowski, P., Bednar, T., Stout, D., Gould, S., and Cohn, J. 2002. Managing power and performance for system-on-chip designs using voltage islands. Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, 195--202.

Digital Library

[18]

Liang, X., Canal, R., Wei, G.-Y., and Brooks, D. 2007. Process variation tolerant 3t1d-based cache architectures. In Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'07). 15--26.

Digital Library

[19]

Marculescu, D. and Garg, S. 2006. System level process-driven variability analysis for single and multiple voltage-frequency islands. In Proceedings of the International Conference on Computer-Aided Design (ICCAD). 541--546.

Digital Library

[20]

Marculescu, D. and Iyer, A. 2002. Power and performance evaluation of globally asynchronous locally synchronous processors. Proceedings of the 29th International Symposium on Computer Architecture (ISCA-02). 30, 158--168.

Digital Library

[21]

Marculescu, D. and Talpes, E. 2005. Variability and energy awareness: a microarchitecture-level perspective. In Proceedings of the 42nd Annual Conference on Design Automation. 11--16.

Digital Library

[22]

Mathur, A., Dasdan, A., and Gupta, R. 1998. Rate analysis for embedded systems. ACM Trans. Des. Automat. Electron. Syst. 3, 3, 408--436.

Digital Library

[23]

Nassif, S. 2000. Design for manufacturability in DSM technologies. In Proceedings of the IEEE International Symposium on Quality Electronic Design.

Digital Library

[24]

Niyogi, K. and Marculescu, D. 2005a. Speed and voltage selection for GALS systems based on voltage/frequency islands. In Proceedings of the Conference on Asia South Pacific Design Automation. 292--297.

Digital Library

[25]

Niyogi, K. and Marculescu, D. 2005b. System level power and performance modeling of GALS point-to-point communication interfaces. In Proceedings of the International Symposium on Low Power Electronics and Design. 381--386.

Digital Library

[26]

Semeraro, G., Albonesi, D. H., Dropsho, S. G., Magklis, G., Dwarkadas, S., and Scott, M. L. 2002. Dynamic frequency and voltage control for a multiple clock domain microarchitecture. In Proceedings of the 35th Annual ACM/IEEE International Symposium on Microarchitecture (MICRO'35).

Digital Library

[27]

Stanley-Marbell, P. and Marculescu, D. 2007. Sunflower: Full-system, embedded microarchitecture evaluation. In Proceedings of the International Conference on High Performance Embedded Architectures and Compilers (HiPEAC).

Digital Library

[28]

Stuijk, S., Geilen, M., and Basten, T. 2006. SDF 3: SDF for free. In Proceedings of the 6th International Conference on Application of Concurrency to System Design. 276--278.

Digital Library

[29]

Teodorescu, R., Nakano, J., Tiwari, A., and Torrellas, J. 2007. Mitigating parameter variation with dynamic fine-grain body biasing. In Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'07). 27--42.

Digital Library

[30]

Tiwari, A., Sarangi, S. R., and Torrellas, J. 2007. Recycle:: pipeline adaptation to tolerate process variation. In Proceedings of the 34th annual international symposium on Computer architecture (ISCA'07). 323--334.

Digital Library

[31]

Tschanz, J., Kao, J., Narendra, S., Nair, R., Antoniadis, D., Chandrakasan, A., and De, V. 2002. Adaptive Body Bias for Reducing Impacts of Die-to-Die. IEEE J. Solid-State Circ. 37, 11.

[32]

Wang, F., Nicopoulos, C., Wu, X., Xie, Y., and Vijaykrishnan, N. 2007. Variation-aware task allocation and scheduling for mpsoc. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. 598--603.

Digital Library

[33]

Wang, F., Wu, X., and Xie, Y. 2008. Variability-driven module selection with joint design time optimization and post-silicon tuning. In Proceedings of the Conference on Asia and South Pacific Design Automation. 2--9.

Digital Library

[34]

Zhan, Y., Strojwas, A., Li, X., Pileggi, L., Newmark, D., and Sharma, M. 2005. Correlation-aware statistical timing analysis with non-gaussian delay distributions. In Proceedings of the 42nd Annual Conference on Design Automation, 77--82.

Digital Library

Cited By

Mercati PPaterna FBartolini AImani MBenini LRosing TCoskun AMargala MBehjat LHan J(2016)VarDroidProceedings of the 26th edition on Great Lakes Symposium on VLSI10.1145/2902961.2902971(269-274)Online publication date: 18-May-2016
https://dl.acm.org/doi/10.1145/2902961.2902971
Kozhikkottu VVenkatesan RRaghunathan ADey S(2016)Emulation-Based Analysis of System-on-Chip Performance Under VariationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.255124324:12(3401-3414)Online publication date: 1-Dec-2016
https://dl.acm.org/doi/10.1109/TVLSI.2016.2551243
Chen KChen JKriebel FRehman SShafique MHenkel J(2016)Task Mapping for Redundant Multithreading in Multi-Cores with Reliability and Performance HeterogeneityIEEE Transactions on Computers10.1109/TC.2016.253286265:11(3441-3455)Online publication date: 1-Nov-2016
https://dl.acm.org/doi/10.1109/TC.2016.2532862
Show More Cited By

Index Terms

System-level throughput analysis for process variation aware multiple voltage-frequency island designs
1. Hardware
  1. Hardware validation

Recommendations

Technology-driven limits on DVFS controllability of multiple voltage-frequency island designs: a system-level perspective
DAC '09: Proceedings of the 46th Annual Design Automation Conference

In this paper, we consider the case of network-on-chip (NoC) based multiple-processor systems-on-chip (MPSoCs) implemented using multiple voltage and frequency islands (VFIs) that rely on fine-grained dynamic voltage and frequency scaling (DVFS) for run-...
Hardware based frequency/voltage control of voltage frequency island systems
CODES+ISSS '06: Proceedings of the 4th international conference on Hardware/software codesign and system synthesis

The ability to do fine grain power management via local voltage selection has shown much promise via the use of Voltage/Frequency Islands (VFIs). VFI-based designs combine the advantages of using fine-grain speed and voltage control for reducing energy ...
System-level process-driven variability analysis for single and multiple voltage-frequency island systems
ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

The problem of determining bounds for application completion times running on generic systems comprised of single or multiple voltage-frequency islands (VFIs) with arbitrary topologies is addressed in the context of manufacturing-driven variability. The ...

Comments

Information & Contributors

Information

Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 13, Issue 4

September 2008

328 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/1391962

Issue’s Table of Contents

Copyright © 2008 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 03 October 2008

Accepted: 01 May 2008

Revised: 01 January 2008

Received: 01 April 2007

Published in TODAES Volume 13, Issue 4

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed

Funding Sources

Semiconductor Research Corporation

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

19
Total Citations
View Citations
448
Total Downloads

Downloads (Last 12 months)2
Downloads (Last 6 weeks)1

Reflects downloads up to 17 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

Mercati PPaterna FBartolini AImani MBenini LRosing TCoskun AMargala MBehjat LHan J(2016)VarDroidProceedings of the 26th edition on Great Lakes Symposium on VLSI10.1145/2902961.2902971(269-274)Online publication date: 18-May-2016
https://dl.acm.org/doi/10.1145/2902961.2902971
Kozhikkottu VVenkatesan RRaghunathan ADey S(2016)Emulation-Based Analysis of System-on-Chip Performance Under VariationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.255124324:12(3401-3414)Online publication date: 1-Dec-2016
https://dl.acm.org/doi/10.1109/TVLSI.2016.2551243
Chen KChen JKriebel FRehman SShafique MHenkel J(2016)Task Mapping for Redundant Multithreading in Multi-Cores with Reliability and Performance HeterogeneityIEEE Transactions on Computers10.1109/TC.2016.253286265:11(3441-3455)Online publication date: 1-Nov-2016
https://dl.acm.org/doi/10.1109/TC.2016.2532862
Mirzoyan DAkesson BStuijk SGoossens K(2015)Maximizing the Number of Good Dies for Streaming Applications in NoC-Based MPSoCs Under Process VariationACM Transactions on Embedded Computing Systems10.1145/278596814:4(1-26)Online publication date: 24-Sep-2015
https://dl.acm.org/doi/10.1145/2785968
Kamal MAfzali-Kusha ASafari SPedram M(2014)Impact of Process Variations on Speedup and Maximum Achievable Frequency of Extensible ProcessorsACM Journal on Emerging Technologies in Computing Systems10.1145/256766510:3(1-25)Online publication date: 6-May-2014
https://dl.acm.org/doi/10.1145/2567665
Arjomand MBoroumand ASarbazi-Azad H(2014)A generic FPGA prototype for on-chip systems with network-on-chip communication infrastructureComputers and Electrical Engineering10.1016/j.compeleceng.2013.11.03140:1(158-167)Online publication date: 1-Jan-2014
https://dl.acm.org/doi/10.1016/j.compeleceng.2013.11.031
Wanner LElmalaki SLai LGupta PSrivastava MMarculescu RPanda P(2013)VarEMUProceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis10.5555/2555692.2555719(1-10)Online publication date: 29-Sep-2013
https://dl.acm.org/doi/10.5555/2555692.2555719
Garg SMarculescu D(2013)Mitigating the Impact of Process Variation on the Performance of 3-D Integrated CircuitsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.222676221:10(1903-1914)Online publication date: 1-Oct-2013
https://dl.acm.org/doi/10.1109/TVLSI.2012.2226762
Mirzoyan DStuijk SAkesson BGoossens K(2013)Throughput analysis and Voltage-Frequency Island partitioning for streaming applications under process variationThe 11th IEEE Symposium on Embedded Systems for Real-time Multimedia10.1109/ESTIMedia.2013.6704497(1-10)Online publication date: Oct-2013
https://doi.org/10.1109/ESTIMedia.2013.6704497
Wanner LElmalaki SLiangzhen Lai Gupta PSrivastava M(2013)VarEMU: An emulation testbed for variability-aware software2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)10.1109/CODES-ISSS.2013.6659014(1-10)Online publication date: Sep-2013
https://doi.org/10.1109/CODES-ISSS.2013.6659014
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Issue’s Table of Contents