research-article

A practical reconfigurable hardware accelerator for Boolean satisfiability solvers

Authors:

Lintao ZhangAuthors Info & Claims

DAC '08: Proceedings of the 45th annual Design Automation Conference

Pages 780 - 785

https://doi.org/10.1145/1391469.1391669

Published: 08 June 2008 Publication History

Abstract

We present a practical FPGA-based accelerator for solving Boolean Satisfiability problems (SAT). Unlike previous efforts for hardware accelerated SAT solving, our design focuses on accelerating the most time consuming part of the SAT solver --- Boolean Constraint Propagation (BCP), leaving the choices of heuristics such as branching order, restarting policy, and learning and backtracking to software. Our novel approach uses an application-specific architecture instead of an instance-specific one to avoid time-consuming FPGA synthesis for each SAT instance. By avoiding global signal wires and carefully pipelining the design, our BCP accelerator is able to achieve much higher clock frequency than that of previous work. In addition, it can load SAT instances in milliseconds, can handle SAT instances with tens of thousands of variables and clauses using a single FPGA, and can easily scale to handle more clauses by using multiple FPGAs. Our evaluation on a cycle-accurate simulator shows that the FPGA co-processor can achieve 3.7--38.6x speedup on BCP compared to state-of-the-art software SAT solvers.

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Cited By

Govindasamy HEsfandiari BGarcia P(2024)Accelerating Boolean Constraint Propagation for Efficient SAT-Solving on FPGAsProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3658808(305-309)Online publication date: 12-Jun-2024
https://dl.acm.org/doi/10.1145/3649476.3658808
Zamiri Azar KMardani Kamali HFarahmandi FTehranipoor MZamiri Azar KMardani Kamali HFarahmandi FTehranipoor M(2023)Impact of Satisfiability Solvers on Logic LockingUnderstanding Logic Locking10.1007/978-3-031-37989-5_7(131-154)Online publication date: 23-Sep-2023
https://doi.org/10.1007/978-3-031-37989-5_7
Chen HFu CZhao JKoushanfar F(2022)GALU: A Genetic Algorithm Framework for Logic UnlockingDigital Threats: Research and Practice10.1145/34912564:2(1-30)Online publication date: 18-Feb-2022
https://dl.acm.org/doi/10.1145/3491256
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Index Terms

A practical reconfigurable hardware accelerator for Boolean satisfiability solvers
1. Computer systems organization
  1. Embedded and cyber-physical systems
  2. Real-time systems

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cover image ACM Conferences

DAC '08: Proceedings of the 45th annual Design Automation Conference

June 2008

993 pages

ISBN:9781605581156

DOI:10.1145/1391469

General Chair:
Limor Fix
Intel Research Pittsburgh, Pittsburgh, PA

Copyright © 2008 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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The EDA Consortium
IEEE/CASS/CANDE/CEDA
SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

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Published: 08 June 2008

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DAC '08

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DAC '08: The 45th Annual Design Automation Conference 2008

June 8 - 13, 2008

California, Anaheim

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

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Cited By

Govindasamy HEsfandiari BGarcia P(2024)Accelerating Boolean Constraint Propagation for Efficient SAT-Solving on FPGAsProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3658808(305-309)Online publication date: 12-Jun-2024
https://dl.acm.org/doi/10.1145/3649476.3658808
Zamiri Azar KMardani Kamali HFarahmandi FTehranipoor MZamiri Azar KMardani Kamali HFarahmandi FTehranipoor M(2023)Impact of Satisfiability Solvers on Logic LockingUnderstanding Logic Locking10.1007/978-3-031-37989-5_7(131-154)Online publication date: 23-Sep-2023
https://doi.org/10.1007/978-3-031-37989-5_7
Chen HFu CZhao JKoushanfar F(2022)GALU: A Genetic Algorithm Framework for Logic UnlockingDigital Threats: Research and Practice10.1145/34912564:2(1-30)Online publication date: 18-Feb-2022
https://dl.acm.org/doi/10.1145/3491256
Kinzer SKim JGhodrati SYatham BAlthoff AMahajan DLerner SEsmaeilzadeh H(2021)A Computational Stack for Cross-Domain Acceleration2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA51647.2021.00015(54-70)Online publication date: Feb-2021
https://doi.org/10.1109/HPCA51647.2021.00015
Bohm Agostini NDong SKarimi ETorrents Lapuerta MCano JAbellan JKaeli D(2020)Design Space Exploration of Accelerators and End-to-End DNN Evaluation with TFLITE-SOC2020 IEEE 32nd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)10.1109/SBAC-PAD49847.2020.00013(10-19)Online publication date: Sep-2020
https://doi.org/10.1109/SBAC-PAD49847.2020.00013
Narasimharaju DRao RWaingade AYasin ACiesielski M(2020)Dual Approach to Solving SAT in Hardware2020 15th Design & Technology of Integrated Systems in Nanoscale Era (DTIS)10.1109/DTIS48698.2020.9081088(1-6)Online publication date: Apr-2020
https://doi.org/10.1109/DTIS48698.2020.9081088
Skliarova ISklyarov VSkliarova ISklyarov V(2019)Architectures of FPGA-Based Hardware Accelerators and Design TechniquesFPGA-BASED Hardware Accelerators10.1007/978-3-030-20721-2_2(39-67)Online publication date: 31-May-2019
https://doi.org/10.1007/978-3-030-20721-2_2
Ustaoglu BHuhn SGroße DDrechsler RChen DHomayoun HTaskin B(2018)SAT-LancerProceedings of the 2018 Great Lakes Symposium on VLSI10.1145/3194554.3194643(479-482)Online publication date: 30-May-2018
https://dl.acm.org/doi/10.1145/3194554.3194643
Yin XSedighi BVarga MErcsey-Ravasz MToroczkai ZHu X(2018)Efficient Analog Circuits for Boolean SatisfiabilityIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.275419226:1(155-167)Online publication date: Jan-2018
https://doi.org/10.1109/TVLSI.2017.2754192
Wijesinghe PLiyanagedera CRoy K(2018)Analog Approach to Constraint Satisfaction Enabled by Spin Orbit Torque Magnetic Tunnel JunctionsScientific Reports10.1038/s41598-018-24877-z8:1Online publication date: 2-May-2018
https://doi.org/10.1038/s41598-018-24877-z
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