tutorial

Technology, CAD tools, and designs for emerging 3D integration technology

Authors:

Syed M. Alam,

Mike Ignatowski,

Yuan XieAuthors Info & Claims

GLSVLSI '08: Proceedings of the 18th ACM Great Lakes symposium on VLSI

Pages 1 - 2

https://doi.org/10.1145/1366110.1366112

Published: 04 May 2008 Publication History

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Abstract

Because of continued advancements in process technology, three-dimensional (3D) integration with stacked chips is emerging as a promising solution to meet the challenges of high-performance, differentiated technology integration, and smaller form factor in complex System-on-a-Chip (SoC) design. High density vertical connections between stacked strata reduce well-known interconnect delay issues and increases interconnect bandwidth in a 3D chip. Adding the third dimension to design opens up new opportunities for EDA tools and design/architectural techniques to fully explore new approaches and address the challenges of 3D integration.

This tutorial will discuss following key topics in 3D integration: -Overview of 3D integration process: Through-Si via, die-on-wafer, wafer-on-wafer bonding -Market applications and drivers for 3D integration -Design techniques for cost-effective 3D integration: 3D IP reuse, design-for-test -Thermal issues in 3D -CAD tools and algorithms for 3D IC design -3D microprocessor design -3D multi-core architectures with network-on-chip

Cited By

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Ling JLi HXu GXiong L(2014)Stochastic wire-length model with TSV placement on periphery area2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)10.1109/EPTC.2014.7028291(5-10)Online publication date: Dec-2014
https://doi.org/10.1109/EPTC.2014.7028291
Kumar AReddy SBecker BPomeranz I(2012)Performance aware partitioning for 3D-SOCs2012 International SoC Design Conference (ISOCC)10.1109/ISOCC.2012.6407065(163-166)Online publication date: Nov-2012
https://doi.org/10.1109/ISOCC.2012.6407065
Kumar AReddy SPomeranz IBecker B(2011)Hyper-graph based partitioning to reduce DFT cost for pre-bond 3D-IC testing2011 Design, Automation & Test in Europe10.1109/DATE.2011.5763230(1-6)Online publication date: Mar-2011
https://doi.org/10.1109/DATE.2011.5763230

Index Terms

Technology, CAD tools, and designs for emerging 3D integration technology
1. Hardware
  1. Integrated circuits

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Published In

GLSVLSI '08: Proceedings of the 18th ACM Great Lakes symposium on VLSI

May 2008

480 pages

ISBN:9781595939999

DOI:10.1145/1366110

General Chairs:
Vijay Narayanan
Penn State University
,
Zhiyuan Yan
Lehigh University
,
Program Chairs:
Enrico Macii
Politecnico di Torino
,
Sanjukta Bhanja
University of South Florida

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 04 May 2008

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GLSVLSI08

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GLSVLSI08: Great Lakes Symposium on VLSI 2008

May 4 - 6, 2008

Florida, Orlando, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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GLSVLSI '25

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sigda

Great Lakes Symposium on VLSI 2025

June 30 - July 2, 2025

New Orleans , LA , USA

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Cited By

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Ling JLi HXu GXiong L(2014)Stochastic wire-length model with TSV placement on periphery area2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)10.1109/EPTC.2014.7028291(5-10)Online publication date: Dec-2014
https://doi.org/10.1109/EPTC.2014.7028291
Kumar AReddy SBecker BPomeranz I(2012)Performance aware partitioning for 3D-SOCs2012 International SoC Design Conference (ISOCC)10.1109/ISOCC.2012.6407065(163-166)Online publication date: Nov-2012
https://doi.org/10.1109/ISOCC.2012.6407065
Kumar AReddy SPomeranz IBecker B(2011)Hyper-graph based partitioning to reduce DFT cost for pre-bond 3D-IC testing2011 Design, Automation & Test in Europe10.1109/DATE.2011.5763230(1-6)Online publication date: Mar-2011
https://doi.org/10.1109/DATE.2011.5763230

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Recommendations

A Test Integration Methodology for 3D Integrated Circuits

The Potential of Emerging Technology for Social Change

Perspectives on technology and technology-driven CAD

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