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Virtual execution of AADL models via a translation into synchronous programs

Published: 30 September 2007 Publication History

Abstract

Architecture description languages are used to describe both the hardware and software architecture of an application, at system-level. The basic software components are intended to be developed independently, and then deployed on the described architecture. This separate development of the architecture and of the software raises the problem of early validation of the integrated system.
In this paper, we propose to solve this problem by translating the architecture into an executable model, which can be simulated and validated together with the software components. More specifically, we consider the case where the architecture is described in the AADL language, and the software components are developed in some synchronous language like Scade or Lustre. We show how the architecture can be automatically translated into a non-deterministic synchronous model, to which the actual software component can be integrated. The result is an executable integrated synchronous model, which can be validated with tools available for synchronous programs. The approach is illustrated on an industrial case study extracted from an actual spatial system.

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cover image ACM Conferences
EMSOFT '07: Proceedings of the 7th ACM & IEEE international conference on Embedded software
September 2007
304 pages
ISBN:9781595938251
DOI:10.1145/1289927
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 30 September 2007

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Author Tags

  1. architecture description language
  2. formal verification
  3. simulation
  4. synchronous languages

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ESWEEK07
ESWEEK07: Third Embedded Systems Week
September 30 - October 3, 2007
Salzburg, Austria

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Overall Acceptance Rate 60 of 203 submissions, 30%

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