Article

Speculative supplier identification for reducing power of interconnects in snoopy cache coherence protocols

Authors:

Ehsan Atoofian,

Amirali Baniasadi,

Kaveh AasaraaiAuthors Info & Claims

CF '07: Proceedings of the 4th international conference on Computing frontiers

Pages 259 - 266

https://doi.org/10.1145/1242531.1242568

Published: 07 May 2007 Publication History

Abstract

In this work we reduce interconnect power dissipation in Symmetric Multiprocessors or SMPs. We revisit snoopy cache coherence protocols and reduce unnecessary interconnect activity by speculating nodes expected to provide a missing data. Conventional snoopy cache coherence protocols broadcast requests to all nodes, reducing the latency of cache to cache transfer misses at the expense of increasing interconnect power. We show that it is possible to reduce the associated power dissipation if such requests are broadcasted selectively and only to nodes more likely to provide the missing data. We reduce power as we limit access only to the interconnect components between the requester and the supplier node. We evaluate our technique using shared memory applications and show that it is possible to reduce interconnect power by 21% in a 4-way multiprocessor without compromising performance. This comes with negligible hardware overhead.

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Cited By

Ranganathan ABayrak AKluter TBrisk PCharbon EIenne P(2012)Counting stream registers: An efficient and effective snoop filter architecture2012 International Conference on Embedded Computer Systems (SAMOS)10.1109/SAMOS.2012.6404165(120-127)Online publication date: Jul-2012
https://doi.org/10.1109/SAMOS.2012.6404165

Index Terms

Speculative supplier identification for reducing power of interconnects in snoopy cache coherence protocols
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Interconnection architectures

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Published In

cover image ACM Conferences

CF '07: Proceedings of the 4th international conference on Computing frontiers

May 2007

300 pages

ISBN:9781595936837

DOI:10.1145/1242531

General Chairs:
Utpal Banerjee
Intel, USA
,
José Moreira
IBM, USA
,
Program Chairs:
Michel Dubois
University of Southern California, USA
,
Per Stenström
Chalmers University of Technology, SE

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 07 May 2007

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May 7 - 9, 2007

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Overall Acceptance Rate 273 of 785 submissions, 35%

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Cited By

Ranganathan ABayrak AKluter TBrisk PCharbon EIenne P(2012)Counting stream registers: An efficient and effective snoop filter architecture2012 International Conference on Embedded Computer Systems (SAMOS)10.1109/SAMOS.2012.6404165(120-127)Online publication date: Jul-2012
https://doi.org/10.1109/SAMOS.2012.6404165

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