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An efficient delay test generation system for combinational logic circuits

Authors:

M. Ray MercerAuthors Info & Claims

DAC '90: Proceedings of the 27th ACM/IEEE Design Automation Conference

Pages 522 - 528

https://doi.org/10.1145/123186.123390

Published: 03 January 1991 Publication History

Abstract

This paper presents an efficient delay test generation system for combinational logic circuits. Delay testing problems are divided into gross delay fault testing and small delay fault testing in order to explore the trade-off between the levels of delay testing effort and the confidence levels of proper system operation. Complete automatic test pattern generation algorithms are proposed for both gross delay faults and small delay faults. Especially for the small delay fault test generation, new search space enumeration techniques are employed so as to bias the search space such that a delay test for relatively long paths can be found. Also a novel timing analysis method via functionality check is presented for delay test generation. Finally, complete test results are demonstrated for both gross delay faults and small delay faults on several benchmark circuits.

References

[1]

E. P. Hsieh, R. A. Rasmussen, L. J. Vidunas, and W. T. Davis, " Delay Test Generation," Proc. 14th Design Automation Conf., pp. 486-491, June 1977.

Digital Library

[2]

G.L. Smith, " Model for Delay Faults Based upon Path," Proc. lnt. Test Conf., pp. 342-349, 1985.

[3]

C.J. Lin and S. M. Reddy, " On Delay Fault Testing in Logic Circuits," IEEETrans. on CAD, pp. 694-703, September 1987.

[4]

E.S. Park arid M. R. Mercer, "Robust arid Nonrobust Tests for Path Delay Faults in a Combinational Circuit," Proc. Ira. Test Conf., pp. 1027-1034, 198"/.

[5]

J. Savir, and W. H. McAnney, " Random Pattern Testability of Delay Fault," IEEE Trans. on Computers, Voi.37, No.3, pp. 291-300, March 1988.

Digital Library

[6]

J. A. Waicukauski, E. Lindbloom, B. Rosen, and V. Iyengar, " Transition Fault Simulation by Parallel Pattern Single Fault Propagation," Proc. Int. Test Conf., pp. 542-549, 1986.

[7]

P. Goel, "An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits," IEEE Trans. on Comput., Vol.30, No.3, pp. 215-222, 1981.

Digital Library

[8]

A.K. Pramanick and S. M. Reddy, "On the Detection of Delay Faults," Proc. Int. Test Conf., pp. 8,*5-856, 1988.

[9]

V.S. {yengar, B. K. Rosen, and i. Spillinger, "Delay Test Generation 2-- Algebra and Algorithms," Proc. Int. Test Conf., pp. 867-874, 1988.

[10]

C. T. Glover and M. R. Mercer, "A Deterministic Approach to Adjacency Testing for Delay Faults," Proc. 26th Design Automation Conf., pp.351-.356, 1989.

Digital Library

[11]

E. S. Park, "Delay Fault Testing: Figure of Merit and Test Generation," Ph.D. dissertation, Dep. Elec. Comput. Eng., Univ. of Texas, Austin, 1989.

[12]

V. S. Iyengar, B. K. Rosen, and I. Spillinger, "Delay Test Generation i-- Concepts and Coverage Metrics," Proc. Int. Test Conf., pp. 857-866, 1988.

[13]

E. S. Park, M. R. Mercer, and T. W. Williams, "Statistical Delay Fault Coverage and Defect Level for Delay Faults," Proc. Int. Test Conf., pp. 492-499, 1988.

[14]

E. S. Park, M. R. Mercer, and T. W. Williams, "A Statistical Model for Delay Fault Coverage," 1EEE Design and Test of Computers, pp.45-55, February 1989.

Digital Library

[15]

R. B. Hitchcock, R. A. Rasmussen, L J. Vidunas, and W. T. Davis, "Timing Analysis of Computer Hardwares," IBM J. Res. Develop., Vol.26, No.I, pp.100-105, 1982.

Digital Library

[16]

T. Kirkland and M. R. Mercer, "A Topological Search Algorithm for ATPG," Proc. 24th Design Automation Conf., pp.502-508, 1987.

Digital Library

[17]

D. Harel, "A Linear Algorithm for Finding Dominators in Flow Graphs and Related Problems," Proc. 17th A CM Syrup. on the Theory of Comtiting, pp.185-194, 1985.

Digital Library

[18]

H. Fujiwara and T. Shimono, "On the Acceleration of Test Generation Algorithms," IEEE Trans. on Comput., pp.223-234, 1980.

[19]

F. B rglez and H. Fujiwara, "Neutral Netlist of Ten Combinational Benchmark Circuits and a Target Translator in FORTRAN," Special session on ATPG and fault simulation, Proc. IEEE Int. Syrup. on Circuits and Systems, June 1985.

Cited By

Jafarzadeh HKlemme FReimer JNajafi-Haghi ZAmrouch HHellebrand SWunderlich H(2023)Robust Pattern Generation for Small Delay Faults Under Process Variations2023 IEEE International Test Conference (ITC)10.1109/ITC51656.2023.00026(111-116)Online publication date: 7-Oct-2023
https://doi.org/10.1109/ITC51656.2023.00026
Takahashi HWatanabe TMatsunaga TTakamatsu Y(1997)Tests for small gate delay faults in combinational circuits and a test generation methodSystems and Computers in Japan10.1002/(SICI)1520-684X(19970615)28:6<68::AID-SCJ8>3.0.CO;2-K28:6(68-76)Online publication date: 15-Jun-1997
https://doi.org/10.1002/(SICI)1520-684X(19970615)28:6<68::AID-SCJ8>3.0.CO;2-K
Mao WCiletti MMusgrave G(1992)A quantitative measure of robustness for delay fault testingProceedings of the conference on European design automation10.5555/159754.161806(543-549)Online publication date: 1-Nov-1992
https://dl.acm.org/doi/10.5555/159754.161806
Show More Cited By

Index Terms

An efficient delay test generation system for combinational logic circuits
1. Hardware
  1. Hardware test
    1. Test-pattern generation and fault simulation
  2. Integrated circuits
    1. Logic circuits
      1. Combinational circuits

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cover image ACM Conferences

DAC '90: Proceedings of the 27th ACM/IEEE Design Automation Conference

January 1991

742 pages

ISBN:0897913639

DOI:10.1145/123186

Chairman:
Richard C. Smith

Copyright © 1991 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 03 January 1991

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DAC90: The 27th ACM/IEEE-CS Design Automation Conference

June 24 - 27, 1990

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DAC '90 Paper Acceptance Rate 125 of 427 submissions, 29%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Jafarzadeh HKlemme FReimer JNajafi-Haghi ZAmrouch HHellebrand SWunderlich H(2023)Robust Pattern Generation for Small Delay Faults Under Process Variations2023 IEEE International Test Conference (ITC)10.1109/ITC51656.2023.00026(111-116)Online publication date: 7-Oct-2023
https://doi.org/10.1109/ITC51656.2023.00026
Takahashi HWatanabe TMatsunaga TTakamatsu Y(1997)Tests for small gate delay faults in combinational circuits and a test generation methodSystems and Computers in Japan10.1002/(SICI)1520-684X(19970615)28:6<68::AID-SCJ8>3.0.CO;2-K28:6(68-76)Online publication date: 15-Jun-1997
https://doi.org/10.1002/(SICI)1520-684X(19970615)28:6<68::AID-SCJ8>3.0.CO;2-K
Mao WCiletti MMusgrave G(1992)A quantitative measure of robustness for delay fault testingProceedings of the conference on European design automation10.5555/159754.161806(543-549)Online publication date: 1-Nov-1992
https://dl.acm.org/doi/10.5555/159754.161806
Mao WCiletti MNewton A(1991)Correlation-reduced scan-path design to improve delay fault coverageProceedings of the 28th ACM/IEEE Design Automation Conference10.1145/127601.127631(73-79)Online publication date: 1-Jun-1991
https://dl.acm.org/doi/10.1145/127601.127631

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