Article

Free access

Comparing structurally different views of a VLSI design

Author:

Mike SpreitzerAuthors Info & Claims

DAC '90: Proceedings of the 27th ACM/IEEE Design Automation Conference

Pages 200 - 212

https://doi.org/10.1145/123186.123258

Published: 03 January 1991 Publication History

PDF eReader

Abstract

In large design projects, it is desirable to compare alternate views that use different hierarchies. However, existing techniques either require essentially identical hierarchies (which is sometimes an unacceptable restriction) or must flatten to remove the differences (which may be very costly). A new technique, Informed Comparison, has neither shortcoming. First, hierarchy transformations are applied to reconcile the structures of the views; then a hierarchical base comparison finishes the task. The reconciliation is guided by a small amount of additional design information: the intended relationship between the hierarchies of the views. Some qualities of Informed Comparison depend on the reconciliation repertoire and the base comparison. Two examples are studied.

References

[1]

Richard Barth, Louis Monler, Bertrand Serlet, and Pradeep Sindhu. VLSI design aids: Capture, integration, and layout generation. Xerox Polo Alto Research Center, July 1988.

Google Scholar

[2]

Carl Ebeling and Ofer Zajicek. Validating VLSI circuit layout by wirelist comparison. IEEE International Conference on Computer-Aided Design, 1983.

Google Scholar

[3]

John E. Hopcroft and Jeffrey D. Ullman. Introduction to Automata Theory, Languages, and Computation. Addison-Wesley, 1979.

Digital Library

Google Scholar

[4]

Mark Horowitz, John L. Hennessy, Paul Chow, P. Glenn Gulak, John M. Acken, Anant Agarwal, Chorng-Yeung Chu, Scott A. McFarling, Steven A. Przybylski, Steve E. Richardson, arturo Salz, Richard T. Simoni, Don C. Stark, Peter A. Steenkiste, Steve W. K. Tjiang, and Malcolm J. Wing. A 32b microprocessor with on-chip 2K byte instruction cache. IEEE International Solid-State Circuits Conference, February 1987.

Google Scholar

[5]

Mike Spreitzer. Comparing Structurally Different Views of a VLSI Design. PhD thesis, Stanford University, 1989.

Digital Library

Google Scholar

[6]

Makoto Takashima, Takashi Mitsuhashi, Toshiaki Chiba, and Kenji Yoshida. Programs for verifying circuit connectivity of MOS / LSI mask artwork. ACM IEEE 19th Design Automation Conference, 1982.

Digital Library

Google Scholar

[7]

J. D. Tygar and Ron Ellickson. Efficient netlist comparison using hierarchy and randomization. ACM IEEE 22nd Design Automation Conference, 1985.

Digital Library

Google Scholar

[8]

Valid Logic Systems. COMPARE reference manual. SCALD star Release 9.1. San Jose, CA, 1 April 1987.

Google Scholar

[9]

Daniel Weise. Formal verification of MOS circuits. ACM IEEE 24th Design Automation Conference, 1987.

Digital Library

Google Scholar

Cited By

View all

Pelz GRoettcher U(2006)Pattern matching and refinement hybrid approach to circuit comparisonIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.25994913:2(264-276)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.259949
Wonjong Kim Hyunchul Shin (1998)Hierarchical LVS based on hierarchy rebuildingProceedings of 1998 Asia and South Pacific Design Automation Conference10.1109/ASPDAC.1998.669504(379-384)Online publication date: 1998
https://doi.org/10.1109/ASPDAC.1998.669504
Mir SFiler NMermet J(1994)Re-engineering hardware specifications by exploiting design semanticsProceedings of the conference on European design automation10.5555/198174.198279(336-341)Online publication date: 23-Sep-1994
https://dl.acm.org/doi/10.5555/198174.198279
Show More Cited By

Index Terms

Comparing structurally different views of a VLSI design
1. Hardware
  1. Hardware validation
    1. Functional verification
  2. Very large scale integration design

Recommendations

Comments

Information & Contributors

Information

Published In

DAC '90: Proceedings of the 27th ACM/IEEE Design Automation Conference

January 1991

742 pages

ISBN:0897913639

DOI:10.1145/123186

Chairman:
Richard C. Smith

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 03 January 1991

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

DAC90

Sponsor:

SIGDA
IEEE-CS

DAC90: The 27th ACM/IEEE-CS Design Automation Conference

June 24 - 27, 1990

Florida, Orlando, USA

Acceptance Rates

DAC '90 Paper Acceptance Rate 125 of 427 submissions, 29%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

5
Total Citations
View Citations
296
Total Downloads

Downloads (Last 12 months)35
Downloads (Last 6 weeks)4

Reflects downloads up to 01 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Pelz GRoettcher U(2006)Pattern matching and refinement hybrid approach to circuit comparisonIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.25994913:2(264-276)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.259949
Wonjong Kim Hyunchul Shin (1998)Hierarchical LVS based on hierarchy rebuildingProceedings of 1998 Asia and South Pacific Design Automation Conference10.1109/ASPDAC.1998.669504(379-384)Online publication date: 1998
https://doi.org/10.1109/ASPDAC.1998.669504
Mir SFiler NMermet J(1994)Re-engineering hardware specifications by exploiting design semanticsProceedings of the conference on European design automation10.5555/198174.198279(336-341)Online publication date: 23-Sep-1994
https://dl.acm.org/doi/10.5555/198174.198279
Nair RChickermane VChamberlain RAmbler TJess JDe Man H(1991)Restructuring VLSI layout representations for efficiencyProceedings of the conference on European design automation10.5555/951513.951538(111-116)Online publication date: 25-Feb-1991
https://dl.acm.org/doi/10.5555/951513.951538
Nair RChickermane VChamberlain R(1991)Restructuring VLSI layout representations for efficiencyProceedings of the European Conference on Design Automation.10.1109/EDAC.1991.206371(111-116)Online publication date: 1991
https://doi.org/10.1109/EDAC.1991.206371

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Comparing structurally different views on a VLSI design

Multilevel circuit partitioning for computer-aided vlsi design

Automatic design planning and exploration of vlsi systems