Structured and tuned array generation (STAG) for high-performance random logic
Authors: 
Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kosonocky, Zhenyu (Jerry) Qi, Mircea R. StanAuthors Info & Claims
Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kosonocky, Zhenyu (Jerry) Qi, Mircea R. StanAuthors Info & ClaimsPages 257 - 262
Abstract
Regularly structured design techniques can combat complexity on a variety of fronts. We present the Structured and Tuned Array Generation (STAG) design methodology, which provides a complete design solution from logic to layout for regularly structured circuits. The STAG circuit tuning constraints are a key component of the methodology. The tuning contraints first guide a SPICE-level tuner to a violation free region in the design space. Secondly, the tuning methodology provides flexibility for targeting a variety of design contraints and objectives. Design examples illustrate STAG's ability for fast turnaround time as well as for high performance and timing critical random logic.
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Index Terms
- Structured and tuned array generation (STAG) for high-performance random logic
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Published In
March 2007
626 pages
ISBN:9781595936059
DOI:10.1145/1228784
- General Chairs:
- Hai Zhou,
- Enrico Macii,
- Program Chairs:
- Zhiyuan Yan,
- Yehia Massoud
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Published: 11 March 2007
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