Article

A practical FPGA-based framework for novel CMP research

Authors:

Njuguna Njoroge,

Christos Kozyrakis,

Kunle OlukotunAuthors Info & Claims

FPGA '07: Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays

Pages 116 - 125

https://doi.org/10.1145/1216919.1216936

Published: 18 February 2007 Publication History

Abstract

Chip-multiprocessors are quickly gaining momentum in all segments of computing. However, the practical success of CMPs strongly depends on addressing the difficulty of multithreaded application development. To address this challenge, it is necessary to co-develop new CMP architecture with novel programming models. Currently, architecture research relies on software simulators which are too slow to facilitate interesting experiments with CMP software without using small datasets or significantly reducing the level of detail in the simulated models. An alternative to simulation is to exploit the rich capabilities of modern FPGAs to create FPGA-based platforms for novel CMP research. This paper presents ATLAS, the first prototype for CMPs with hardware support for Transactional Memory (TM), a technology aiming to simplify parallel programming. ATLAS uses the BEE2 multi-FPGA board to provide a system with 8 PowerPC cores that run at 100MHz and runs Linux. ATLAS provides significant benefits for CMP research such as 100x performance improvement over a software simulator and good visibility that helps with software tuning and architectural improvements. In addition to presenting and evaluating ATLAS, we share our observations about building a FPGA-based framework for CMP research. Specifically, we address issues such as overall performance, challenges of mapping ASIC-style CMP RTL on to FPGAs, software support, the selection criteria for the base processor, and the challenges of using pre-designed IP libraries.

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Karandikar SOu AAmid AMao HKatz RNikolić BAsanović KLarus JCeze LStrauss K(2020)FirePerfProceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3373376.3378455(715-731)Online publication date: 9-Mar-2020
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Index Terms

A practical FPGA-based framework for novel CMP research
1. Computing methodologies
  1. Modeling and simulation
    1. Model development and analysis
      1. Modeling methodologies

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cover image ACM Conferences

FPGA '07: Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays

February 2007

248 pages

ISBN:9781595936004

DOI:10.1145/1216919

General Chair:
André DeHon
University of Pennsylvania, USA
,
Program Chair:
Mike Hutton
Altera, USA

Copyright © 2007 ACM.

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Published: 18 February 2007

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FPGA07: ACM/SIGDA International Symposium on Field Programmable Gate Arrays 2007

February 18 - 20, 2007

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

Lan MHuang LYang LMa SYan RWang YXu W(2022)Late-Stage Optimization of Modern ILP Processor Cores via FPGA SimulationApplied Sciences10.3390/app12231222512:23(12225)Online publication date: 29-Nov-2022
https://doi.org/10.3390/app122312225
Karandikar SOu AAmid AMao HKatz RNikolić BAsanović KLarus JCeze LStrauss K(2020)FirePerfProceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3373376.3378455(715-731)Online publication date: 9-Mar-2020
https://dl.acm.org/doi/10.1145/3373376.3378455
Abeydeera MSanchez DLarus JCeze LStrauss K(2020)Chronos: Efficient Speculative Parallelism for AcceleratorsProceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3373376.3378454(1247-1262)Online publication date: 9-Mar-2020
https://dl.acm.org/doi/10.1145/3373376.3378454
Venkataramanan VLakshmi SKanetkar V(2019)Design and implementation of LTE physical layer on FPGAInternational Journal of Computer Applications in Technology10.1504/ijcat.2019.10211161:1-2(127-134)Online publication date: 1-Jan-2019
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Reddy B PM V(2019)Crack Detection Robot in Underground Gas Pipelines using FPGA2019 IEEE 5th International Conference for Convergence in Technology (I2CT)10.1109/I2CT45611.2019.9033781(1-5)Online publication date: Mar-2019
https://doi.org/10.1109/I2CT45611.2019.9033781
Ceriani MSecchi SVilla OTumeo APalermo G(2017)Exploring Efficient Hardware Support for Applications with Irregular Memory Patterns on Multinode Manycore ArchitecturesIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2014.234507328:6(1635-1648)Online publication date: 1-Jun-2017
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Chen XZhang GWang HWu RWu PZhang LNebel WAtienza D(2015)MRPProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2755799(211-216)Online publication date: 9-Mar-2015
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Dhawan UDehon A(2015)Area-Efficient Near-Associative Memories on FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/26294717:4(1-22)Online publication date: 23-Jan-2015
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Tessier RPocek KDeHon A(2015)Reconfigurable Computing ArchitecturesProceedings of the IEEE10.1109/JPROC.2014.2386883103:3(332-354)Online publication date: Mar-2015
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Mori HKise K(2014)Design and Performance Evaluation of a Manycore Processor for Large FPGAProceedings of the 2014 IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs10.1109/MCSoC.2014.37(207-214)Online publication date: 23-Sep-2014
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