Article

A defect tolerant self-organizing nanoscale SIMD architecture

Authors:

Jaidev P. Patwardhan,

Alvin R. LebeckAuthors Info & Claims

ASPLOS XII: Proceedings of the 12th international conference on Architectural support for programming languages and operating systems

Pages 241 - 251

https://doi.org/10.1145/1168857.1168888

Published: 20 October 2006 Publication History

Abstract

The continual decrease in transistor size (through either scaled CMOS or emerging nano-technologies) promises to usher in an era of tera to peta-scale integration. However, this decrease in size is also likely to increase defect densities, contributing to the exponentially increasing cost of top-down lithography. Bottom-up manufacturing techniques, like self assembly, may provide a viable lower-cost alternative to top-down lithography, but may also be prone to higher defects. Therefore, regardless of fabrication methodology, defect tolerant architectures are necessary to exploit the full potential of future increased device densities.This paper explores a defect tolerant SIMD architecture. A key feature of our design is the ability of a large number of limited capability nodes with high defect rates (up to 30%) to self-organize into a set of SIMD processing elements. Despite node simplicity and high defect rates, we show that by supporting the familiar data parallel programming model the architecture can execute a variety of programs. The architecture efficiently exploits a large number of nodes and higher device densities to keep device switching speeds and power density low. On a medium sized system (~1cm² area), the performance of the proposed architecture on our data parallel programs matches or exceeds the performance of an aggressively scaled out-of-order processor (128-wide, 8k reorder buffer, perfect memory system). For larger systems (>1cm²), the proposed architecture can match the performance of a chip multiprocessor with 16 aggressively scaled out-of-order cores.

References

[1]

H. Abelson et al. Amorphous Computing. Communications of the ACM, 43(5):74--82, 2000.

Digital Library

[2]

T. Austin et al. SimpleScalar: An Infrastructure for Computer System Modeling. IEEE Computer, 35(2):59--67, Feb. 2002

Digital Library

[3]

A. Bachtold et al. Logic Circuits with Carbon Nanotube Transistors. Science, 294:1317--1320, Nov. 2001

[4]

P. J. Burke. Carbon Nanotube Devices for GHz to THz Applications. Proc. of SPIE, 5593:52--61, 2004

[5]

S. Ciricescu et al. The Reconfigurable Streaming Vector Processor (RSVP). Proc. of the 36th Annual IEEE/ACM Int'l Symposium on Microarchitecture, pages 141--150, Dec. 2003

Digital Library

[6]

W. B. Culbertson et al. The Teramac Custom Computer: Extending the Limits with Defect Tolerance. In Proc. of the IEEE Int'l Symposium on Defect and Fault Tolerance in VLSI Systems, Nov. 1996.

Digital Library

[7]

Y. K. Dalal and R. M. Metcalfe. Reverse Path Forwarding of Broadcast Packets. Communications of the ACM, 21(12):1040--1048, 1978.

Digital Library

[8]

A. DeHon. Array-Based Architecture for Molecular Electronics. In Proc. of the First Workshop on Non-Silicon Computation (NSC-1), Feb. 2002.

[9]

C. Dwyer et al. DNA Functionalized Single-Walled Carbon Nanotubes. Nanotechnology, 13:601--604, 2002.

[10]

C. Dwyer. Self-Assembled Computer Architecture: Design and Fabrication Theory. PhD thesis, Univ. of North Carolina, 2003.

Digital Library

[11]

C. Dwyer et al. Semi-empirical SPICE Models for Carbon Nanotube FET Logic. In Proc. of the Fourth IEEE Conference on Nanotechnology, Aug. 2004.

[12]

C. Dwyer et al. The Design and Fabrication of a Fully Addressable 8-tile DNA Lattice. In Foundations of Nanoscience: Self-Assembled Architectures and Devices, pages 187--191, Apr. 2005.

[13]

R. Espasa et al. Tarantula: A Vector Extension to the Alpha Architecture. Proc. of the 29th Annual Int'l Symposium on Computer Architecture, pages 281--292, May 2002.

Digital Library

[14]

S. C. Goldstein and M. Budiu. NanoFabrics: Spatial Computing Using Molecular Electronics. Proc. of the 28th Annual Int'l Symposium on Computer Architecture, pages 178--191, July 2001.

Digital Library

[15]

H. Hofstee. Power Efficient Processor Architecture and The Cell Processor. Proc. of the Eleventh Int'l Symposium on High-Performance Computer Architecture, pages 258--262, Feb. 2005.

Digital Library

[16]

Y. Huang et al. Logic Gates and Computation from Assembled Nanowire Building Blocks. Science, 294:1313--1317, Nov. 2001.

[17]

C. Intanagonwiwat et al. Directed Diffusion: A Scalable and Robust Communication Paradigm for Sensor Networks. In Mobile Computing and Networking, pages 56--67, 2000.

Digital Library

[18]

International Technology Roadmap for Semiconductors, 2005.

[19]

U. Kapasi et al. The Imagine Stream Processor. Proc. IEEE Int'l Conference on Computer Design, pages 282--288, Sept. 2002.

Digital Library

[20]

D.E. Knuth. The Art of Computer Programming. Addison-Wesley, 1973.

Digital Library

[21]

C.E. Leiserson et al. The Network Architecture of the Connection Machine CM-5. Proc. of the Fourth ACM Symposium on Parallel Algorithms and Architectures, pages 272--285, June 1992.

Digital Library

[22]

A. Lines. Asynchronous interconnect for synchronous SoC design. IEEE Micro, 24:32--41, Jan/Feb 2004.

Digital Library

[23]

R. Lyons and W. Vanderkulk. The Use of Triple-Modular Redundancy to Improve Computer Reliability. IBM Journal, pages 200--209, 1962.

Digital Library

[24]

K. Mai et al. Smart Memories: A Modular Reconfigurable Architecture. Proc. of the 27th Annual Int'l Symposium on Computer Architecture, June 2000.

Digital Library

[25]

R. Needham and D. Wheeler. Tea Extensions. Technical report, Computer Laboratory, University of Cambridge, Oct. 1997.

[26]

S.H. Park et al. Finite-size, Fully-Addressable DNA Tile Lattices Formed by Hierarchical Assembly Procedures. Angewandte Chemie, 45:735--739, Jan. 2006.

[27]

J.P. Patwardhan et al. Circuit and System Architecture for DNA-Guided Self-Assembly of Nanoelectronics. Proc. of Foundations of Nanoscience: Self-Assembled Architectures and Devices, pages 344--358, Apr. 2004.

[28]

J.P. Patwardhan et al. Evaluating the Connectivity of Self-Assembled Networks of Nano-scale Processing Elements. In IEEE Int'l Workshop on Design and Test of Defect-Tolerant Nanoscale Architectures (NANOARCH '05), pages 2.1--2.8, May 2005.

[29]

J.P. Patwardhan et al. Design and Evaluation of Fail-Stop Self-Assembled Nanoscale Processing Elements. In IEEE Int'l Workshop on Design and Test of Defect-Tolerant Nanoscale Architectures (NANOARCH '06), June 2006.

[30]

J.P. Patwardhan et al. NANA: A Nano-scale Active Network Architecture. ACM Journal on Emerging Technologies in Computing Systems, 2(1):1--30, 2006.

Digital Library

[31]

J. P. Patwardhan et al. Self-Assembled Networks: Control vs. Complexity. 1st Int'l Conference on Nano-Networks, Sept. 2006.

[32]

Performance Database Server. http://www.netlib.org/performance/html/PDStop.html.

[33]

B.H. Robinson and N.C. Seeman. The design of a biochop: a self-assembling molecular-scale memory device. Protein Engineering, 1:295--300, Aug. 1987.

[34]

S. Rosenblatt et al. Mixing at 50GHz using a Single-Walled Carbon Nanotube Transistor. Applied Physics Letters, 87:153111, Oct. 2005.

[35]

M.D. Schroeder et al. Autonet: A High-speed, Self-Configuring Local Area Network Using Point to Point Links. IEEE Journal on Selected Areas in Communications, 9(8), Oct. 1991.

Digital Library

[36]

K. Skinner et al. Nanowire Transistors, Gate Electrodes, and Their Directed Self-Assembly. In The 72nd Southeastern Section of the American Physical Society (SESAPS), Nov. 2005.

[37]

J. von Neumann. Probabilistic Logics and the Synthesis of Reliable Organisms from Unreliable Components. In C.Shannon and J. McCarthy, editors, Automata Studies, pages 43-98. Princeton University Press, Princeton, NJ, 1956.

[38]

D. Wheeler and R. Needham. TEA: A Tiny Encryption Algorithm. In Fast Software Encryption: Second Int'l Workshop, Dec. 1994.

[39]

E. Winfree et al. Design and Self-Assembly of Two-Dimensional DNA Crystals. Nature, 394:539, 1998.

[40]

H. Yan et al. DNA Templated Self-Assembly of Protein Arrays and Highly Conductive Nanowires. Science, 301(5641):1882--1884, Sept. 2003.

Cited By

Patel RParekh R(2019)DNA Based Hybrid Circuit Design Approaches2019 IEEE 5th International Conference for Convergence in Technology (I2CT)10.1109/I2CT45611.2019.9034066(1-6)Online publication date: Mar-2019
https://doi.org/10.1109/I2CT45611.2019.9034066
Patel JMakvana KShah P(2019)Cross-lingual Information Retrieval: application and Challenges for Indian Languages2019 IEEE 5th International Conference for Convergence in Technology (I2CT)10.1109/I2CT45611.2019.9033563(1-4)Online publication date: Mar-2019
https://doi.org/10.1109/I2CT45611.2019.9033563
Czeizler EOrponen P(2015)Fault Tolerant Design and Analysis of Carbon Nanotube Circuits Affixed on DNA Origami TilesIEEE Transactions on Nanotechnology10.1109/TNANO.2015.245567314:5(871-877)Online publication date: 1-Sep-2015
https://dl.acm.org/doi/10.1109/TNANO.2015.2455673
Show More Cited By

Index Terms

A defect tolerant self-organizing nanoscale SIMD architecture
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Multiple instruction, multiple data
2. Hardware
  1. Integrated circuits
    1. Interconnect
    2. Logic circuits

Recommendations

A defect tolerant self-organizing nanoscale SIMD architecture
Proceedings of the 2006 ASPLOS Conference

The continual decrease in transistor size (through either scaled CMOS or emerging nano-technologies) promises to usher in an era of tera to peta-scale integration. However, this decrease in size is also likely to increase defect densities, contributing ...
A defect tolerant self-organizing nanoscale SIMD architecture
Proceedings of the 2006 ASPLOS Conference

The continual decrease in transistor size (through either scaled CMOS or emerging nano-technologies) promises to usher in an era of tera to peta-scale integration. However, this decrease in size is also likely to increase defect densities, contributing ...
A defect tolerant self-organizing nanoscale SIMD architecture
Proceedings of the 2006 ASPLOS Conference

The continual decrease in transistor size (through either scaled CMOS or emerging nano-technologies) promises to usher in an era of tera to peta-scale integration. However, this decrease in size is also likely to increase defect densities, contributing ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ASPLOS XII: Proceedings of the 12th international conference on Architectural support for programming languages and operating systems

October 2006

440 pages

ISBN:1595934510

DOI:10.1145/1168857

General Chair:
John Paul Shen
Intel Corp.
,
Program Chair:
Margaret R. Martonosi
Princeton University

ACM SIGARCH Computer Architecture News Volume 34, Issue 5
Proceedings of the 2006 ASPLOS Conference
December 2006
425 pages
ISSN:0163-5964
DOI:10.1145/1168919
Issue’s Table of Contents
ACM SIGOPS Operating Systems Review Volume 40, Issue 5
Proceedings of the 2006 ASPLOS Conference
December 2006
425 pages
ISSN:0163-5980
DOI:10.1145/1168917
Issue’s Table of Contents
ACM SIGPLAN Notices Volume 41, Issue 11
Proceedings of the 2006 ASPLOS Conference
November 2006
425 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/1168918
Issue’s Table of Contents

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 20 October 2006

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

ASPLOS06

Sponsor:

ASPLOS06: Architectural Support for Programming Languages and Operating Systems

October 21 - 25, 2006

California, San Jose, USA

Acceptance Rates

ASPLOS XII Paper Acceptance Rate 38 of 158 submissions, 24%;

Overall Acceptance Rate 535 of 2,713 submissions, 20%

Upcoming Conference

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

25
Total Citations
View Citations
916
Total Downloads

Downloads (Last 12 months)5
Downloads (Last 6 weeks)0

Reflects downloads up to 04 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

Patel RParekh R(2019)DNA Based Hybrid Circuit Design Approaches2019 IEEE 5th International Conference for Convergence in Technology (I2CT)10.1109/I2CT45611.2019.9034066(1-6)Online publication date: Mar-2019
https://doi.org/10.1109/I2CT45611.2019.9034066
Patel JMakvana KShah P(2019)Cross-lingual Information Retrieval: application and Challenges for Indian Languages2019 IEEE 5th International Conference for Convergence in Technology (I2CT)10.1109/I2CT45611.2019.9033563(1-4)Online publication date: Mar-2019
https://doi.org/10.1109/I2CT45611.2019.9033563
Czeizler EOrponen P(2015)Fault Tolerant Design and Analysis of Carbon Nanotube Circuits Affixed on DNA Origami TilesIEEE Transactions on Nanotechnology10.1109/TNANO.2015.245567314:5(871-877)Online publication date: 1-Sep-2015
https://dl.acm.org/doi/10.1109/TNANO.2015.2455673
(2010)SCW 2009 Invited KeynoteProceedings of the 2010 Fourth IEEE International Conference on Self-Adaptive and Self-Organizing Systems Workshop10.1109/SASOW.2010.81(xxviii-xxx)Online publication date: 27-Sep-2010
https://dl.acm.org/doi/10.1109/SASOW.2010.81
Garcia SOrailoǧlu ABenini LDe Micheli GAl-Hashimi BMueller W(2009)Making DNA self-assembly error-proofProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874839(898-901)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874839
Liu BWakabayashi K(2009)Reconfigurable double gate carbon nanotube field effect transistor based nanoelectronic architectureProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509822(853-858)Online publication date: 19-Jan-2009
https://dl.acm.org/doi/10.5555/1509633.1509822
Pistol CChongchitmate WDwyer CLebeck A(2009)Architectural implications of nanoscale integrated sensing and computingACM SIGARCH Computer Architecture News10.1145/2528521.150824737:1(13-24)Online publication date: 7-Mar-2009
https://dl.acm.org/doi/10.1145/2528521.1508247
Pistol CChongchitmate WDwyer CLebeck A(2009)Architectural implications of nanoscale integrated sensing and computingACM SIGPLAN Notices10.1145/1508284.150824744:3(13-24)Online publication date: 7-Mar-2009
https://dl.acm.org/doi/10.1145/1508284.1508247
Pistol CChongchitmate WDwyer CLebeck ASoffa MIrwin M(2009)Architectural implications of nanoscale integrated sensing and computingProceedings of the 14th international conference on Architectural support for programming languages and operating systems10.1145/1508244.1508247(13-24)Online publication date: 7-Mar-2009
https://dl.acm.org/doi/10.1145/1508244.1508247
Liu B(2009)Defect Mapping and Adaptive Configuration of Nanoelectronic Circuits Based on a CNT Crossbar Nano-ArchitectureProceedings of the 2009 Proceedings of 18th International Conference on Computer Communications and Networks10.1109/ICCCN.2009.5235271(1-6)Online publication date: 3-Aug-2009
https://dl.acm.org/doi/10.1109/ICCCN.2009.5235271
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents