Article

Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation

Authors:

Wolfgang NebelAuthors Info & Claims

ISLPED '06: Proceedings of the 2006 international symposium on Low power electronics and design

Pages 220 - 225

https://doi.org/10.1145/1165573.1165628

Published: 04 October 2006 Publication History

Abstract

In this work we present a SPICE-based RTL subthreshold-leakage model analyzing components built in 70nm technology [1]. We present a separation approach regarding inter- and intra-die threshold variations, temperature, supply-voltage, and state dependence. The body-effect and differences between NMOS and PMOS introduce a leakage state dependence of one order of magnitude[2, 3]. We show that the leakage of RT-components still shows state dependencies between 20% and $80%. A leakage model not regarding the state can never be more accurate than this. The proposed state aware model has an average error of 6.7% for the RT-components analyzed.

References

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D Helms, M Hoyer, W Nebel: Accurate PTV, State, and ABB Aware RTL Blackbox Modeling of Subthreshold, Gate, and PN-Junction Leakage. PATMOS, 2006.

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Cited By

Grüttner KHartmann PHylla KRosinger SNebel WHerrera FVillar EBrandolese CFornaciari WPalermo GYkman-Couvreur CQuaglia DFerrero FValencia R(2013)The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space explorationMicroprocessors & Microsystems10.1016/j.micpro.2013.09.00137:8(966-980)Online publication date: 1-Nov-2013
https://dl.acm.org/doi/10.1016/j.micpro.2013.09.001
Grüttner KHylla KRosinger SNebel W(2011)Rapid Prototyping of Complex HW/SW Systems using a Timing and Power Aware ESL FrameworkSystem Specification and Design Languages10.1007/978-1-4614-1427-8_10(157-173)Online publication date: 8-Nov-2011
https://doi.org/10.1007/978-1-4614-1427-8_10
Medardoni SBertozzi DMacii EMarculescu DRaghunathan AKeshavarzi ANarayanan V(2007)Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologiesProceedings of the 2007 international symposium on Low power electronics and design10.1145/1283780.1283815(159-164)Online publication date: 27-Aug-2007
https://dl.acm.org/doi/10.1145/1283780.1283815
Show More Cited By

Index Terms

Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation
1. Hardware
  1. Hardware validation

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Published In

cover image ACM Conferences

ISLPED '06: Proceedings of the 2006 international symposium on Low power electronics and design

October 2006

446 pages

ISBN:1595934626

DOI:10.1145/1165573

General Chairs:
Wolfgang Nebel
University of Oldenburg and OFFIS
,
Mircea Stan
University of Virginia
,
Anand Raghunathan
NEC Laboratories America
,
Program Chairs:
Joerg Henkel
University of Karlsruhe
,
Diana Marculescu
Carnegie Mellon University

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 04 October 2006

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ISLPED06: International Symposium on Low Power Electronics and Design

October 4 - 6, 2006

Bavaria, Tegernsee, Germany

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

Grüttner KHartmann PHylla KRosinger SNebel WHerrera FVillar EBrandolese CFornaciari WPalermo GYkman-Couvreur CQuaglia DFerrero FValencia R(2013)The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space explorationMicroprocessors & Microsystems10.1016/j.micpro.2013.09.00137:8(966-980)Online publication date: 1-Nov-2013
https://dl.acm.org/doi/10.1016/j.micpro.2013.09.001
Grüttner KHylla KRosinger SNebel W(2011)Rapid Prototyping of Complex HW/SW Systems using a Timing and Power Aware ESL FrameworkSystem Specification and Design Languages10.1007/978-1-4614-1427-8_10(157-173)Online publication date: 8-Nov-2011
https://doi.org/10.1007/978-1-4614-1427-8_10
Medardoni SBertozzi DMacii EMarculescu DRaghunathan AKeshavarzi ANarayanan V(2007)Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologiesProceedings of the 2007 international symposium on Low power electronics and design10.1145/1283780.1283815(159-164)Online publication date: 27-Aug-2007
https://dl.acm.org/doi/10.1145/1283780.1283815
Heloue KAzizi NNajm FLevitan S(2007)Modeling and estimation of full-chip leakage current considering within-die correlationProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278504(93-98)Online publication date: 4-Jun-2007
https://dl.acm.org/doi/10.1145/1278480.1278504
Helms DHoyer MNebel W(2006)Accurate PTV, state, and ABB aware RTL blackbox modeling of subthreshold, gate, and PN-Junction leakageProceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation10.1007/11847083_6(56-65)Online publication date: 13-Sep-2006
https://dl.acm.org/doi/10.1007/11847083_6

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