Article

Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction

Authors:

Yan Lin,

Fei Li,

Lei HeAuthors Info & Claims

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Pages 645 - 650

https://doi.org/10.1145/1120725.1120984

Published: 18 January 2005 Publication History

Get Access

Abstract

Power has become an increasingly important design constraint for FPGAs in nanometer technologies, and global interconnects should be the focus of FPGA power reduction as they consume more power than logic cells. We design area-efficient circuits for programmable fine-grained power-gating of individual unused interconnect switches, and reduce interconnect leakage power dramatically because the interconnect switches have an intrinsically low utilization rate for the purpose of programmability. The low leakage interconnect via power-gating reduces total power by 38.18% for the FPGA in 100nm technology. Furthermore, it enables interconnect dynamic power reduction. We design a routing channel containing abundant or duplicated routing tracks with pre-determined high and low Vdd, and develop routing algorithm using low Vdd for non-critical routing to reduce dynamic power. The track-duplicated routing channel has small leakage power and increase the FPGA power reduction to 45.00%.

References

[1]

K. Poon, A. Yan, and S. Wilton, "A flexible power model for FPGAs," in Proc. of 12th International conference on Field-Programmable Logic and Applications, Sep 2002.

Digital Library

Google Scholar

[2]

F. Li, D. Chen, L. He, and J. Cong, "Architecture evaluation for power-efficient FPGAs," in Proc. ACM Intl. Symp. Field-Programmable Gate Arrays, Feb 2003.

Digital Library

Google Scholar

[3]

T. Tuan and B. Lai, "Leakage power analysis of a 90nm FPGA," in Proc. IEEE CICC, 2003.

Crossref

Google Scholar

[4]

J. H. Anderson, F. N. Najm, and T. Tuan, "Active leakage power optimization for FPGAs," in Proc. ACM Intl. Symp. Field-Programmable Gate Arrays, Februray 2004.

Digital Library

Google Scholar

[5]

A. Gayasen, Y. Tsai, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, and T. Tuan, "Reducing leakage energy in FPGAs using region-constrained placement," in Proc. ACM Intl. Symp. Field-Programmable Gate Arrays, February 2004.

Digital Library

Google Scholar

[6]

F. Li, Y. Lin, L. He, and J. Cong, "Low-power FPGA using pre-defined dual-vdd/dual-vt fabrics," in Proc. ACM Intl. Symp. Field-Programmable Gate Arrays, Februray 2004.

Digital Library

Google Scholar

[7]

F. Li, Y. Lin, and L. He, "FPGA power reduction using configurable dual-vdd," in Proc. Design Automation Conf., June 2004.

Digital Library

Google Scholar

[8]

E. Kusse and J. Rabaey, "Low-energy embedded FPGA structures," in Proc. Intl. Symp. Low Power Electronics and Design, pp. 155--160, August 1998.

Digital Library

Google Scholar

[9]

Fei Li, Yan Lin and Lei He, "Vdd programmability to reduce fpga interconnect power," in Proc. Intl. Conf. Computer-Aided Design, November 2004.

Digital Library

Google Scholar

[10]

G. G. Lemieux et. al., "A detailed router for allocating wire segments in field-programmable gate arrays," in Proceedings of the ACM Physical Design Workshop, April 1993.

Google Scholar

[11]

V. Betz et. al., Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Publishers, Feb 1999.

Digital Library

Google Scholar

[12]

R. W. Brodersen et. al., "Methods for ture power minimization," in Proc. Intl. Conf. Computer-Aided Design, pp. 35--42, 2002.

Digital Library

Google Scholar

Cited By

View all

Rai SNath PRupani AVishvakarma SKumar A(2021)A Survey of FPGA Logic Cell Designs in the Light of Emerging TechnologiesIEEE Access10.1109/ACCESS.2021.30921679(91564-91574)Online publication date: 2021
https://doi.org/10.1109/ACCESS.2021.3092167
Seifoori ZAsadi HStojilovic M(2021)Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced RoutingIEEE Access10.1109/ACCESS.2021.30850059(115599-115619)Online publication date: 2021
https://doi.org/10.1109/ACCESS.2021.3085005
Seifoori ZAsadi HStojilovic M(2019)A Machine Learning Approach for Power Gating the FPGA Routing Network2019 International Conference on Field-Programmable Technology (ICFPT)10.1109/ICFPT47387.2019.00010(10-18)Online publication date: Dec-2019
https://doi.org/10.1109/ICFPT47387.2019.00010
Show More Cited By

Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction
1. Hardware

Recommendations

Optimizing effective interconnect capacitance for FPGA power reduction
FPGA '14: Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays

We propose a technique to reduce the effective parasitic capacitance of interconnect routing conductors in a bid to simultaneously reduce power consumption and improve delay. The parasitic capacitance reduction is achieved by ensuring routing conductors ...
Vdd programmability to reduce FPGA interconnect power
ICCAD '04: Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

Power is an increasingly important design constraint for FPGAs in nanometer technologies. Because interconnect power is dominant in FPGAs, we design Vdd-programmable interconnect fabric to reduce FPGA interconnect power. There are three Vdd states for ...
Fine-grained supply gating through hypergraph partitioning and Shannon decomposition for active power reduction
DATE '08: Proceedings of the conference on Design, automation and test in Europe

Energy-efficient performance has emerged as the key design objective of high-performance logic circuits to address power-induced reliability concerns and battery life requirements in portable devices. In the sub-65nm technology regime, these problems ...

Comments

Information & Contributors

Information

Published In

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

January 2005

1495 pages

ISBN:0780387376

DOI:10.1145/1120725

General Chair:
Ting-Ao Tang
Fudan University, Shanghai, P. R. China

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 January 2005

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

ASPDAC05

Sponsor:

SIGDA

ASPDAC05: Asia and South Pacific Design Automation Conference

January 18 - 21, 2005

Shanghai, China

Acceptance Rates

Overall Acceptance Rate 466 of 1,454 submissions, 32%

Upcoming Conference

ASPDAC '25

Sponsor:
sigda

30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

Tokyo , Japan

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

30
Total Citations
View Citations
374
Total Downloads

Downloads (Last 12 months)3
Downloads (Last 6 weeks)0

Reflects downloads up to 26 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Rai SNath PRupani AVishvakarma SKumar A(2021)A Survey of FPGA Logic Cell Designs in the Light of Emerging TechnologiesIEEE Access10.1109/ACCESS.2021.30921679(91564-91574)Online publication date: 2021
https://doi.org/10.1109/ACCESS.2021.3092167
Seifoori ZAsadi HStojilovic M(2021)Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced RoutingIEEE Access10.1109/ACCESS.2021.30850059(115599-115619)Online publication date: 2021
https://doi.org/10.1109/ACCESS.2021.3085005
Seifoori ZAsadi HStojilovic M(2019)A Machine Learning Approach for Power Gating the FPGA Routing Network2019 International Conference on Field-Programmable Technology (ICFPT)10.1109/ICFPT47387.2019.00010(10-18)Online publication date: Dec-2019
https://doi.org/10.1109/ICFPT47387.2019.00010
Williams SLin MAnderson JBazargan K(2018)Architecture and Circuit Design of an All-Spintronic FPGAProceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3174243.3174256(41-50)Online publication date: 15-Feb-2018
https://dl.acm.org/doi/10.1145/3174243.3174256
Seifoori ZKhaleghi BAsadi H(2017)A power gating switch box architecture in routing network of SRAM-based FPGAs in dark silicon eraProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130696(1342-1347)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130696
Seifoori ZKhaleghi BAsadi H(2017)A power gating switch box architecture in routing network of SRAM-based FPGAs in dark silicon eraDesign, Automation & Test in Europe Conference & Exhibition (DATE), 201710.23919/DATE.2017.7927201(1342-1347)Online publication date: Mar-2017
https://doi.org/10.23919/DATE.2017.7927201
Nag APradhan S(2017)An Autonomous Power and Clock Gating Technique in SRAM-Based FPGAProceedings of the International Conference on Nano-electronics, Circuits & Communication Systems10.1007/978-981-10-2999-8_1(1-14)Online publication date: 25-Mar-2017
https://doi.org/10.1007/978-981-10-2999-8_1
HIOKI MKOIKE H(2016)Low Overhead Design of Power Reconfigurable FPGA with Fine-Grained Body Biasing on 65-nm SOTB CMOS TechnologyIEICE Transactions on Information and Systems10.1587/transinf.2016EDP7129E99.D:12(3082-3089)Online publication date: 2016
https://doi.org/10.1587/transinf.2016EDP7129
Bsoul AWilton STsoi KLuk W(2016)An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power GatingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.239391424:1(178-191)Online publication date: Jan-2016
https://doi.org/10.1109/TVLSI.2015.2393914
Hioki MMa CKawanami TOgasahara YNakagawa TSekigawa TTsutsumi TKoike H(2014)SOTB Implementation of a Field Programmable Gate Array with Fine-Grained Vt ProgrammabilityJournal of Low Power Electronics and Applications10.3390/jlpea40301884:3(188-200)Online publication date: 15-Jul-2014
https://doi.org/10.3390/jlpea4030188
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Recommendations

Optimizing effective interconnect capacitance for FPGA power reduction

Vdd programmability to reduce FPGA interconnect power

Fine-grained supply gating through hypergraph partitioning and Shannon decomposition for active power reduction

Comments

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Qualifiers

Conference

Acceptance Rates

Upcoming Conference

Other Metrics

Article Metrics

Other Metrics

Cited By

Login options

Full Access

PDF

eReader

Abstract

References

Cited By

Recommendations

Optimizing effective interconnect capacitance for FPGA power reduction

Vdd programmability to reduce FPGA interconnect power

Fine-grained supply gating through hypergraph partitioning and Shannon decomposition for active power reduction

Comments

Information

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Qualifiers

Conference

Acceptance Rates

Upcoming Conference

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

Login options

Full Access

View options

PDF

eReader

Figures

Other

Share

Share this Publication link

Share on social media

Affiliations