article

Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths

Author:

Masahiro FujitaAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 10, Issue 4

Pages 610 - 626

https://doi.org/10.1145/1109118.1109121

Published: 01 October 2005 Publication History

Abstract

In this article, we present techniques for comparison between behavioral level and register transfer level (RTL) design descriptions by mapping the designs into virtual controllers and virtual datapaths. We also discuss about how the equivalence between behavioral level and RTL designs can be defined precisely using the proposed “attribute statements” in an interactive fashion. Implementation issues as well as considerations on real life industrial design examples are also presented.

References

[1]

Abdi, S., Peng, J., Yu, H., Shin, D.,Gerstlauer, A., Domer, R., and Gajski, D. 2003. System-on-Chip Enviornment: Tutorial. Tech. Rep. CECS-TR-03-41. University of California, Irvine, Irvine, CA.]]

[2]

Anderson, P., Reps, T., Teitelbaum, T., and Zarins, M. 2003. Tool support for fine-grained software inspection. IEEE Softw. 20, 4, 42--50.]]

[3]

Ball, T. and Rajamani, S. K. 2000. Boolean programs: A model and process for software analysis. In Proceedings of the Workshop on Advances in Verification.]]

[4]

Bryant, R. 1986. Graph-based algorithms for Boolean function manipulation. IEEE Trans. Comput. C-35, 8, 677--691.]]

[5]

Clarke, E. M., Fujita, M., Rajan, S. P., Reps, T., Shankar, S., and Teitelbaum, T. 1999. Program slicing for VHDL. In Proceedings of the Conference on Correct Hardware Design and Verification Methods. Lecture Notes in Computer Science, vol. 1703. Springer-Verlag, Berlin, Germany, pp. 298--312.]]

[6]

Clarke, E., Kroening, D., and Yorav, K. 2003. Behavioral consistency of C and Verilog programs using bounded model checking. In Proceedings of the Design Automation Conference. ACM, New York, pp. 368--371.]]

[7]

CodeSurfer. http://www.grammatech.com/products/codesurfer/.]]

[8]

Currie, D. W., Hu, A. J., Rajan, S., and Fujita, M. 2000. Automatic formal verification of DSP software. In Proceedings of the Design Automation Conference. ACM, New York, pp. 130--135.]]

[9]

Fujita, M. and Nakamura, H. 2001. The standard SpecC language. In Proceedings of the International Symposium on System Synthesis. ACM, New York, pp. 81--86.]]

[10]

Gajski, D., Zhu, J., Domer, R., Gerstlauer, A., and Zhao, S. 2000. SpecC: Specification language and Methodology. Kluwer Academic Publishers, 336 p. ISBN: 0-7923-7822-9.]]

[11]

Jain, J., Mukherjee, R., and Fujita, M. 1995. Advanced verification technique based on learning. In Proceedings of the Automation Conference. ACM, New York, pp. 420--426.]]

[12]

Kuehlmann, A. and Krohm, F. 1995. Equivalence checking using cuts and heaps. In Proceedings of the Design Automation Conference. ACM, New York, pp. 263--268.]]

[13]

Matsumoto, T., Saito, H., and Fujita, M. 2004. An equivalence checking methods for C descriptions based on symbolic simulation with textual difference. In Proceedings of the IASTED International Conference on Advances in Computer Science and Technology. ACTA Press, Calgary, Canada.]]

[14]

Moskewicz, M. W., Madigan, C. F., Zhao, Y. Zhang, L. and Malik, S. 2001. Chaff: Engineering an efficient SAT solver. In Proceedings of the Design Automation Conference. ACM, New York.]]

[15]

Ritter, G. 2000. Formal sequential equivalence checking of digital systems by symbolic simulation. Ph.D. dissertation. Darmastadt University of Technology and Université Joseph Fourier.]]

[16]

Ritter, G., Eveking, H., and Hinrichsen, H. 1999. Formal verification of designs with complex control by symbolic simulation. In Proceedings of the Conference on Correct Hardware Design and Verification Methods. Lecture Notes in Computer Science, vol. 1703, Springer-Verlag, Berlin, Germany, pp. 234--249.]]

[17]

Semeria, L., Seawright, A., Mehra, R., Ng, D., Ekanayake, A., and Pangrle, B. 2002. C-based RTL methodology for designing and verifying a multi-threaded processor. In Proceedings of the Design Automation Conference. ACM, New York, pp. 123--128.]]

[18]

SpecC. http://www.cecs.uci.edu/~specc/.]]

[19]

SoC Environment. University of California, Irvine, Irvine, CA. http://www.cecs.uci.edu/~cad/sce.html.]]

[20]

Stump, A., Barret, C., and Dill, D. 2002. CVC: A Cooperating Validity Checker. In Proceedings of the of International Conference on Computer-Aided Verification. Lecture Notes in Computer Science, vol. 2404, Springer-Verlag, Berlin, Germany.]]

[21]

Tanabe, K., Sasaki, S., and Fujita, M. 2004. Program slicing for system level designs in SpecC. In Proceedings of the IASTED International Conference on Advances in Computer Science and Technology. ACTA Press, Calgary, Canada.]]

[22]

Weiser, M. 1979. Program Slices: Formal, Psychological, and Practical Investigations of an Automatic Program Abstraction. ACM, New York.]]

Cited By

Abderehman MPatidar JOza JNigam YKhader TKarfa C(2022)FastSim: A Fast Simulation Framework for High-Level SynthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.309033941:5(1371-1385)Online publication date: May-2022
https://doi.org/10.1109/TCAD.2021.3090339
Campbell KLin DHe LYang LGurumani SRupnow KMitra SChen D(2019)Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level SynthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.283710338:7(1345-1358)Online publication date: Jul-2019
https://doi.org/10.1109/TCAD.2018.2837103
Azarbad MAlizadeh B(2016)Scalable SMT-Based Equivalence Checking of Nested Loop Pipelining in Behavioral SynthesisACM Transactions on Design Automation of Electronic Systems10.1145/295387922:2(1-22)Online publication date: 26-Dec-2016
https://dl.acm.org/doi/10.1145/2953879
Show More Cited By

Index Terms

Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths
1. Hardware
  1. Electronic design automation
    1. Hardware description languages and compilation
  2. Hardware validation
    1. Functional verification

Recommendations

Leveraging sequential equivalence checking to enable system-level to RTL flows
DAC '08: Proceedings of the 45th annual Design Automation Conference

It has long been the practice to create models in C or C++ for architectural studies, software prototyping and RTL verification in the design of Systems-on-Chip (SoC). It is often the case that by the end of a design project, multiple C models exist for ...
An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis

A formal method for checking equivalence between a given behavioral specification prior to scheduling and the one produced by the scheduler is described. Finite state machine with data path (FSMD) models have been used to represent both the behaviors. ...
Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques
ISVLSI '10: Proceedings of the 2010 IEEE Annual Symposium on VLSI

Code motion techniques are extensively used in the pre-synthesis optimization and the scheduling phases of high-level synthesis (HLS) of digital circuits for control intensive behaviours. A formal verification method for checking correctness of code ...

Comments

Information & Contributors

Information

Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 10, Issue 4

October 2005

137 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/1109118

Issue’s Table of Contents

Copyright © 2005 ACM.

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 October 2005

Published in TODAES Volume 10, Issue 4

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

18
Total Citations
View Citations
561
Total Downloads

Downloads (Last 12 months)3
Downloads (Last 6 weeks)0

Reflects downloads up to 14 Sep 2024

Other Metrics

View Author Metrics

Citations

Cited By

Abderehman MPatidar JOza JNigam YKhader TKarfa C(2022)FastSim: A Fast Simulation Framework for High-Level SynthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.309033941:5(1371-1385)Online publication date: May-2022
https://doi.org/10.1109/TCAD.2021.3090339
Campbell KLin DHe LYang LGurumani SRupnow KMitra SChen D(2019)Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level SynthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.283710338:7(1345-1358)Online publication date: Jul-2019
https://doi.org/10.1109/TCAD.2018.2837103
Azarbad MAlizadeh B(2016)Scalable SMT-Based Equivalence Checking of Nested Loop Pipelining in Behavioral SynthesisACM Transactions on Design Automation of Electronic Systems10.1145/295387922:2(1-22)Online publication date: 26-Dec-2016
https://dl.acm.org/doi/10.1145/2953879
Carrion Schafer B(2016)Source Code Error Detection in High-Level Synthesis Functional VerificationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.239703624:1(301-312)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1109/TVLSI.2015.2397036
Campbell KLin DMitra SChen D(2015)Hybrid quick error detection (H-QED)Proceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2753768(1-6)Online publication date: 7-Jun-2015
https://dl.acm.org/doi/10.1145/2744769.2753768
Hu JLi TLi S(2015)Equivalence checking between SLM and TLM using coverage directed simulationFrontiers of Computer Science: Selected Publications from Chinese Universities10.1007/s11704-015-4257-09:6(934-943)Online publication date: 1-Dec-2015
https://dl.acm.org/doi/10.1007/s11704-015-4257-0
Bombieri NFummi FGuarnieri VPravadelli GStefanni FGhasempouri TLora MAuditore GMarcigaglia M(2015)Reusing RTL Assertion Checkers for Verification of SystemC TLM ModelsJournal of Electronic Testing: Theory and Applications10.1007/s10836-015-5514-831:2(167-180)Online publication date: 1-Apr-2015
https://dl.acm.org/doi/10.1007/s10836-015-5514-8
Bombieri NFummi FGuarnieri VPravadelli GStefanni FGhasempouri TLora MAuditore GMarcigaglia M(2014)On the reuse of RTL assertions in SystemC TLM verification2014 15th Latin American Test Workshop - LATW10.1109/LATW.2014.6841903(1-6)Online publication date: Mar-2014
https://doi.org/10.1109/LATW.2014.6841903
Hu JLi TLi S(2013)Equivalence Checking between SLM and TLM Using Coverage Directed SimulationProceedings of the 2013 International Conference on Computer-Aided Design and Computer Graphics10.1109/CADGraphics.2013.21(101-106)Online publication date: 16-Nov-2013
https://dl.acm.org/doi/10.1109/CADGraphics.2013.21
Karfa CMandal CSarkar D(2012)Formal verification of code motion techniques using data-flow-driven equivalence checkingACM Transactions on Design Automation of Electronic Systems10.1145/2209291.220930317:3(1-37)Online publication date: 5-Jul-2012
https://dl.acm.org/doi/10.1145/2209291.2209303
Show More Cited By

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Issue’s Table of Contents