Article

Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications

Authors:

Martin Margala,

Pasquale CorsonelloAuthors Info & Claims

ISLPED '05: Proceedings of the 2005 international symposium on Low power electronics and design

Pages 161 - 166

https://doi.org/10.1145/1077603.1077645

Published: 08 August 2005 Publication History

Abstract

Multimedia applications have become a dominant computing workload for computer systems as well as for wireless-based devices. Due to their repetitive computing and memory intensive nature, they can take effective advantage from Processor-In-Memory (PIM) technology. In this paper, a new low-power PIM-based 32-bit reconfigurable datapath optimized for multimedia applications is presented. The new circuit efficiently performs parallel arithmetic operations on either 8-, 16-, or 32-bit integer data or on 32-bit single precision floating-point data. As a result, high flexibility is provided at a very low hardware cost. When implemented using the UMC 0.18 μm 1.8 V CMOS technology, the proposed datapath exhibits a 285 MHz running frequency, dissipates just 0.12 mW/MHz and occupies a silicon area of only 107,323 μm². When performing 2D-DCT, proposed architecture consumes 74% less power and is 28% more power efficient compared to top-of-the-line commercial TI DSP

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https://doi.org/10.1109/JXCDC.2024.3450810
Su LNaffziger S(2023)1.1 Innovation For the Next Decade of Compute Efficiency2023 IEEE International Solid-State Circuits Conference (ISSCC)10.1109/ISSCC42615.2023.10067810(8-12)Online publication date: 19-Feb-2023
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Index Terms

Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design
    1. Application-specific VLSI designs
      1. Application specific processors

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cover image ACM Conferences

ISLPED '05: Proceedings of the 2005 international symposium on Low power electronics and design

August 2005

400 pages

ISBN:1595931376

DOI:10.1145/1077603

General Chairs:
Kaushik Roy
Purdue University
,
Vivek Tiwari
Intel

Copyright © 2005 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 08 August 2005

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ISLPED05: International Symposium on Low Power Electronics and Design

August 8 - 10, 2005

CA, San Diego, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

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https://doi.org/10.1109/JXCDC.2024.3450810
Su LNaffziger S(2023)1.1 Innovation For the Next Decade of Compute Efficiency2023 IEEE International Solid-State Circuits Conference (ISSCC)10.1109/ISSCC42615.2023.10067810(8-12)Online publication date: 19-Feb-2023
https://doi.org/10.1109/ISSCC42615.2023.10067810
Mosquera CGarzón EPrócel L(2023)Exploiting Dual Mode Logic for Approximate Computing2023 IEEE Seventh Ecuador Technical Chapters Meeting (ECTM)10.1109/ETCM58927.2023.10309002(1-5)Online publication date: 10-Oct-2023
https://doi.org/10.1109/ETCM58927.2023.10309002
Moposita TGarzón EDe Rose RCrupi FVladimirescu ATrojman LLanuzza M(2023)SIMPLY+: A Reliable STT-MRAM-Based Smart Material Implication Architecture for In-Memory ComputingIEEE Access10.1109/ACCESS.2023.334419711(144084-144094)Online publication date: 2023
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Marinberg HGarzón ENoy TLanuzza MTeman A(2023)Efficient Implementation of Many-Ported Memories by Using Standard-Cell Memory ApproachIEEE Access10.1109/ACCESS.2023.331094011(94885-94897)Online publication date: 2023
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Vicuña KMosquera CMusello ABenedictis SRendón MGarzón EPrócel LTrojman LTaco R(2021)Energy Efficient Self-Adaptive Dual Mode Logic Address DecoderElectronics10.3390/electronics1009105210:9(1052)Online publication date: 29-Apr-2021
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Sait AUthayakumar JShankar KKumar K(2019)Introduction to Multimedia Tools and ApplicationsHandbook of Multimedia Information Security: Techniques and Applications10.1007/978-3-030-15887-3_1(3-14)Online publication date: 20-Jul-2019
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Munaf SBharathi DJayanthi D(2016)Double Pumping Low Power Technique for Coarse - Grained Reconfigurable ArchitectureInternational Journal of Electrical and Electronics Research10.37391/IJEER.0401034:1(10-15)Online publication date: 31-Mar-2016
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Alvarez CCorbal JValero M(2012)Dynamic Tolerance Region Computing for MultimediaIEEE Transactions on Computers10.1109/TC.2011.7961:5(650-665)Online publication date: 1-May-2012
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Kim YMahapatra R(2010)Dynamic Context Compression for Low-Power CGRADesign of Low-Power Coarse-Grained Reconfigurable Architectures10.1201/b10471-13(119-140)Online publication date: 9-Dec-2010
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