Article

Normalization at the arithmetic bit level

Authors:

Markus Wedler,

Dominik Stoffel,

Wolfgang KunzAuthors Info & Claims

DAC '05: Proceedings of the 42nd annual Design Automation Conference

Pages 457 - 462

https://doi.org/10.1145/1065579.1065699

Published: 13 June 2005 Publication History

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Abstract

We propose a normalization technique for verifying arithmetic circuits in a bounded model checking environment. Our technique operates on the arithmetic bit level (ABL) description of the arithmetic circuit parts and the property. The ABL description can easily be provided by the front-end of an RTL property checker. The proposed normalization greatly simplifies the SAT instances to be solved for arithmetic circuit verification. Our approach has been applied successfully to verify the integer pipeline of an industrial microprocessor with advanced DSP capabilities.

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Cited By

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Sarbishei ORadecka K(2012)Verification of fixed-point datapaths with comparator units using Constrained Arithmetic Transform (CAT)2012 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2012.6272100(592-595)Online publication date: May-2012
https://doi.org/10.1109/ISCAS.2012.6272100
Alizadeh B(2011)Symbolic model-based diagnosis with auto-correction framework for arithmetic circuits2011 3rd Asia Symposium on Quality Electronic Design (ASQED)10.1109/ASQED.2011.6111744(195-202)Online publication date: Jul-2011
https://doi.org/10.1109/ASQED.2011.6111744
Bryant RKroening DOuaknine JSeshia SStrichman OBrady B(2009)An abstraction-based decision procedure for bit-vector arithmeticInternational Journal on Software Tools for Technology Transfer (STTT)10.5555/3220882.322098411:2(95-104)Online publication date: 1-Apr-2009
https://dl.acm.org/doi/10.5555/3220882.3220984
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Index Terms

Normalization at the arithmetic bit level
1. Hardware
  1. Hardware validation
    1. Functional verification

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Information & Contributors

Information

Published In

DAC '05: Proceedings of the 42nd annual Design Automation Conference

June 2005

984 pages

ISBN:1595930582

DOI:10.1145/1065579

General Chair:
William H. Joyner
IBM Corp./SRC
,
Program Chairs:
Grant E. Martin
Tensilica, Inc.
,
Andrew B. Kahng
University of California at San Diego, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 June 2005

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DAC05: The 42nd Annual Design Automation Conference 2005

June 13 - 17, 2005

California, Anaheim, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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Sarbishei ORadecka K(2012)Verification of fixed-point datapaths with comparator units using Constrained Arithmetic Transform (CAT)2012 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2012.6272100(592-595)Online publication date: May-2012
https://doi.org/10.1109/ISCAS.2012.6272100
Alizadeh B(2011)Symbolic model-based diagnosis with auto-correction framework for arithmetic circuits2011 3rd Asia Symposium on Quality Electronic Design (ASQED)10.1109/ASQED.2011.6111744(195-202)Online publication date: Jul-2011
https://doi.org/10.1109/ASQED.2011.6111744
Bryant RKroening DOuaknine JSeshia SStrichman OBrady B(2009)An abstraction-based decision procedure for bit-vector arithmeticInternational Journal on Software Tools for Technology Transfer (STTT)10.5555/3220882.322098411:2(95-104)Online publication date: 1-Apr-2009
https://dl.acm.org/doi/10.5555/3220882.3220984
Sarbishei OTabandeh MAlizadeh BFujita M(2009)A formal approach for debugging arithmetic circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.201399828:5(742-754)Online publication date: 1-May-2009
https://dl.acm.org/doi/10.1109/TCAD.2009.2013998
Alizadeh BFujita M(2009)Modular arithmetic decision procedure with auto-correction mechanism2009 IEEE International High Level Design Validation and Test Workshop10.1109/HLDVT.2009.5340162(138-145)Online publication date: Nov-2009
https://doi.org/10.1109/HLDVT.2009.5340162
Bryant RKroening DOuaknine JSeshia SStrichman OBrady B(2009)An abstraction-based decision procedure for bit-vector arithmeticInternational Journal on Software Tools for Technology Transfer10.1007/s10009-009-0101-x11:2(95-104)Online publication date: 12-Feb-2009
https://doi.org/10.1007/s10009-009-0101-x
Tew NKalla PShekhar NGopalakrishnan SNassif SRoychowdhury J(2008)Verification of arithmetic datapaths using polynomial function models and congruence solvingProceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design10.5555/1509456.1509494(122-128)Online publication date: 10-Nov-2008
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Krautz UWedler MKunz WWeber KJacobi CPflanz MKyung CChoi KHa S(2008)Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proofProceedings of the 2008 Asia and South Pacific Design Automation Conference10.5555/1356802.1356902(398-403)Online publication date: 21-Jan-2008
https://dl.acm.org/doi/10.5555/1356802.1356902
D'Silva VKroening DWeissenbacher G(2008)A Survey of Automated Techniques for Formal Software VerificationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2008.92341027:7(1165-1178)Online publication date: 1-Jul-2008
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(2008)Arithmetic Circuits Verification without Looking for Internal EquivalencesProceedings of the Sixth ACM/IEEE International Conference on Formal Methods and Models for Co-Design10.1109/MEMCOD.2008.4547681(7-16)Online publication date: 1-Jun-2008
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