article

Efficient techniques for transition testing

Authors:

Michael S. Hsiao,

Sreejit Chakravarty,

Paul J. ThadikaranAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 10, Issue 2

Pages 258 - 278

https://doi.org/10.1145/1059876.1059880

Published: 01 April 2005 Publication History

Abstract

Scan-based transition tests are added to improve the detection of speed failures in sequential circuits. Empirical data suggests that both data volume and application time will increase dramatically for such transition testing. Techniques to address the above problem for a class of transition tests, called enhanced transition tests, are proposed in this article.The first technique, which combines the proposed transition test chains with the ATE repeat capability, reduces test data volume by 46.5% when compared with transition tests computed by a commercial transition test ATPG tool. However, the test application time may sometimes increase. To address the test time issue, a new DFT technique, Exchange Scan, is proposed. Exchange scan reduces both data volume and application time by 46.5%. These techniques rely on the use of hold-scan cells and highlight the effectiveness of hold-scan design to address test time and test data volume issues. In addition, we address the problem of yield loss due to incidental overtesting of functionally-untestable transition faults, and we formulate an efficient adjustment to the algorithm to keep the overtest ratio low. Our experimental results show that up to 14.5% reduction in overtest ratio can be achieved, with an average overtest reduction of 4.68%.

References

[1]

Chandra, A. and Chakrabarty, K. 2001. Frequency directed run length(FDR) codes with application to system on a chip data compression. In Proceedings of the VLSI Testing Symposium. 42--47.

[2]

Dervisoglu, B. and Stong, G. 1991. Design for testability: Using scanpath techniques for path-delay test and measurement. In Proceedings of the IEEE International Test Conference. 365--374.

[3]

Das, D. and Touba, N. A. 2000. Reducing Test Data Volume Using External/BIST Hybrid Test Patterns. In Proceedings of the IEEE International Test Conference. 115--122.

[4]

Eldred, R.D. 1959. Test routing based on symbolic logical statement. J. ACM, 6, 1 (Jan.), 33--36.

[5]

Hsu, F. F., Butler, K. M., and Patel, J. H. 2001. A Case Study of the Illinois scan architecture. In Proceedings of the IEEE International Test Conference. 538--547.

[6]

Hamzaoglu, I. and Patel, J. H. 1999. Reducing Test application time for full scan embedded cores. In 29th International Symposium on Fault-Tolerant Computing. 260--267.

[7]

Heragu, K., Patel, J. H., and Agrawal V. D. 1996. Segment delay faults: a new fault model. In Proceedings of the VLSI Testing Symposium. 32--39.

[8]

Hsiao, M. S. 2002. Maximizing impossibilities for untestable fault identification. In IEEE Design Automation and Test in Europe Conference. 949--953.

[9]

Keller, B., Barnhart, C., Brunkhorst, V., Distler, F., Ferko, A., Farnsworth, O., and Koeneman, B. 2001. OPMISR: The foundation of compressed ATPG vectors. In Proceedings of the IEEE International Test Conference. 748--757.

[10]

Koeneman, B. 1991. LFSR-coded test patterns for scan designs. In IEEE European Test Conference. 237--242.

[11]

Lee, K.-J., Chen, J.,-J., and Huang, C.-H. 1998. Using a single input to support multiple scan chains. In IEEE/ACM International Conference on Computer-Aided Design. 74--78.

[12]

Liu, X., Hsiao, M. S., Chakravarty, S., and Thadikaran, P. J. 2003. Efficient transition fault ATPG algorithms based on stuck-at test vectors. J. Electr. Test. Theo. Applicat., 19, 4 (Aug.), 437--445.

[13]

Lai, W. C., Kristic, A., and Cheng, K. T. 2000a. On testing the path delay faults of a microprocessor using its instrcution set. In Proceedings of the VLSI Testing Symposium. 15--20.

[14]

Lai, W. C., Kristic, A., and Cheng, K. T. 2000b. Test program synthesis for path delay faults in microprocessor cores. In Proceedings of the IEEE International Test Conference. 1080--1089.

[15]

Rearick, J. 2001. Too much delay fault coverage is a bad thing. In Proceedings of the IEEE International Test Conference. 624--633.

[16]

Smith, G. L. 1985. Model for delay faults based upon paths. In Proceedings of the IEEE International Test Conference. 342--349.

[17]

Savir, J. and Patil, S. 1993. Scan-based transition test. IEEE Trans. on Comput.-Aid. Des. Integr. Circuit Syst. 12, 8 (Aug.).

[18]

Savir, J. and Patil, S. 1994. On broad-side delay test. In Proceedings of the VLSI Testing Symposium. 284--290.

[19]

Tendulkar, N., Raina, R., Woltenburg, R., Lin, X., Swanson, B., and Aldrich, G. 2002. Novel techniques for achieving high at-speed transition fault coverage for Motorola's microprocessors based on PowerPC instruction set architecture. In Proceedings of the VLSI Testing Symposium. 3--8.

[20]

Waicukauski, J. A., Lindbloom, E., Rosen, B. K., and Iyengar, V. S. 1987. Transition fault simulation. IEEE Des. Test Comput., (April), 32--38.

Cited By

Xiang DSui WYin BCheng K(2014)Compact Test Generation With an Influence Input Measure for Launch-On-Capture Transition Fault TestingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.228017022:9(1968-1979)Online publication date: Sep-2014
https://doi.org/10.1109/TVLSI.2013.2280170
Pi XKuang JZhang L(2013)Novel pattern selection method for small-delay faults testJOURNAL OF ELECTRONIC MEASUREMENT AND INSTRUMENT10.3724/SP.J.1187.2012.0024226:3(242-247)Online publication date: 6-Feb-2013
https://doi.org/10.3724/SP.J.1187.2012.00242
Xiang DChen ZWang L(2012)Scan Flip-Flop Grouping to Compress Test Data and Compact Test Responses for Launch-on-Capture Delay TestingACM Transactions on Design Automation of Electronic Systems10.1145/2159542.215955017:2(1-24)Online publication date: 1-Apr-2012
https://dl.acm.org/doi/10.1145/2159542.2159550
Show More Cited By

Index Terms

Efficient techniques for transition testing

Recommendations

Generation of Mixed Broadside and Skewed-Load Diagnostic Test Sets for Transition Faults
PRDC '11: Proceedings of the 2011 IEEE 17th Pacific Rim International Symposium on Dependable Computing

This paper describes a diagnostic test generation procedure for transition faults that produces mixed test sets consisting of broadside and skewed-load tests. A mix of broadside and skewed-load tests yields improved diagnostic resolution compared with a ...
Using stuck-at tests to form scan-based tests for transition faults in standard-scan circuits

In enhanced-scan circuits, a two-pattern test < t_i, t_j > for a transition fault can be obtained by using a test t_j that detects a stuck-at fault, and preceding it by a test t_i that activates another stuck-at fault. Thus, test generation for transition ...
Generation of mixed test sets for transition faults

Test sets that contain both broadside and skewed-load tests are important for achieving the highest possible delay fault coverage for standard-scan circuits. Both types of tests can be represented as 〈s₁ v₁, s₂ v₂〉, where s₁ and s₂ are states, and v₁ ...

Comments

Information & Contributors

Information

Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 10, Issue 2

April 2005

244 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/1059876

Issue’s Table of Contents

Copyright © 2005 ACM.

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 April 2005

Published in TODAES Volume 10, Issue 2

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

12
Total Citations
View Citations
375
Total Downloads

Downloads (Last 12 months)3
Downloads (Last 6 weeks)0

Reflects downloads up to 14 Sep 2024

Other Metrics

View Author Metrics

Citations

Cited By

Xiang DSui WYin BCheng K(2014)Compact Test Generation With an Influence Input Measure for Launch-On-Capture Transition Fault TestingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.228017022:9(1968-1979)Online publication date: Sep-2014
https://doi.org/10.1109/TVLSI.2013.2280170
Pi XKuang JZhang L(2013)Novel pattern selection method for small-delay faults testJOURNAL OF ELECTRONIC MEASUREMENT AND INSTRUMENT10.3724/SP.J.1187.2012.0024226:3(242-247)Online publication date: 6-Feb-2013
https://doi.org/10.3724/SP.J.1187.2012.00242
Xiang DChen ZWang L(2012)Scan Flip-Flop Grouping to Compress Test Data and Compact Test Responses for Launch-on-Capture Delay TestingACM Transactions on Design Automation of Electronic Systems10.1145/2159542.215955017:2(1-24)Online publication date: 1-Apr-2012
https://dl.acm.org/doi/10.1145/2159542.2159550
Chen ZXiang D(2010)A novel test application scheme for high transition fault coverage and low test costIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.204835929:6(966-976)Online publication date: 1-Jun-2010
https://dl.acm.org/doi/10.1109/TCAD.2010.2048359
Xiang DYin BCheng K(2009)Dynamic Test Compaction for Transition Faults in Broadside Scan Testing Based on an Influence Cone MeasureProceedings of the 2009 27th IEEE VLSI Test Symposium10.1109/VTS.2009.14(251-256)Online publication date: 3-May-2009
https://dl.acm.org/doi/10.1109/VTS.2009.14
Wang SPeng KHsiao KLi K(2008)Layout-aware scan chain reorder for launch-off-shift transition test coverageACM Transactions on Design Automation of Electronic Systems10.1145/1391962.139197213:4(1-16)Online publication date: 3-Oct-2008
https://dl.acm.org/doi/10.1145/1391962.1391972
Wang STsai PWeng HLi K(2007)Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture16th Asian Test Symposium (ATS 2007)10.1109/ATS.2007.33(95-100)Online publication date: Oct-2007
https://doi.org/10.1109/ATS.2007.33
Lin SLee CChen JChen JLuo KWu W(2006)A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs2006 IEEE International Test Conference10.1109/TEST.2006.297663(1-8)Online publication date: Oct-2006
https://doi.org/10.1109/TEST.2006.297663
Lin YCheng K(2006)A Unified Approach to Test Generation and Test Data Volume Reduction2006 IEEE International Test Conference10.1109/TEST.2006.297644(1-10)Online publication date: Oct-2006
https://doi.org/10.1109/TEST.2006.297644
Kalligeros EKavousianos XNikolos D(2006)Efficient Multiphase Test Set Embedding for Scan-based TestingProceedings of the 7th International Symposium on Quality Electronic Design10.1109/ISQED.2006.56(433-438)Online publication date: 27-Mar-2006
https://dl.acm.org/doi/10.1109/ISQED.2006.56
Show More Cited By

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Issue’s Table of Contents