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Technology decomposition and mapping targeting low power dissipation

Authors:

Chi-Ying Tsui,

Massoud Pedram,

Alvin M. DespainAuthors Info & Claims

DAC '93: Proceedings of the 30th international Design Automation Conference

Pages 68 - 73

https://doi.org/10.1145/157485.164577

Published: 01 July 1993 Publication History

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C. Y. Tsui, M. Pedram, and A. Despain. Technology decomposition and mapping targeting low power dissipation. Technical Report CNEG 92-16, Electrical Engineering-System Department, University of Southern California, October 1992.

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Cited By

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Rout SMahapatro SJayaswal GHooda M(2022)Low‐Power Integrated Circuit Smart Device DesignIntelligent Green Technologies for Sustainable Smart Cities10.1002/9781119816096.ch11(227-246)Online publication date: 23-Aug-2022
https://doi.org/10.1002/9781119816096.ch11
Pasandi GPedram M(2019)PBMap: A Path Balancing Technology Mapping Algorithm for Single Flux Quantum Logic CircuitsIEEE Transactions on Applied Superconductivity10.1109/TASC.2018.288034329:4(1-14)Online publication date: Jun-2019
https://doi.org/10.1109/TASC.2018.2880343
Macii ECalimera AMacii APoncino M(2017) Logic Synthesis of CMOS Circuits and Beyond Nanoelectronics10.1002/9783527800728.ch14(331-362)Online publication date: 7-Apr-2017
https://doi.org/10.1002/9783527800728.ch14
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Index Terms

Technology decomposition and mapping targeting low power dissipation
1. Hardware
  1. Hardware validation
    1. Functional verification
      1. Simulation and emulation
  2. Integrated circuits
    1. Logic circuits
2. Mathematics of computing
  1. Discrete mathematics
    1. Graph theory
      1. Trees

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DAC '93: Proceedings of the 30th international Design Automation Conference

July 1993

768 pages

ISBN:0897915771

DOI:10.1145/157485

Chairman:
Alfred E. Dunlop
AT&T Bell Labs., Murray Hill, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 July 1993

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DAC93: The 30th ACM/IEEE Design Automation Conference

June 14 - 18, 1993

Texas, Dallas, USA

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Rout SMahapatro SJayaswal GHooda M(2022)Low‐Power Integrated Circuit Smart Device DesignIntelligent Green Technologies for Sustainable Smart Cities10.1002/9781119816096.ch11(227-246)Online publication date: 23-Aug-2022
https://doi.org/10.1002/9781119816096.ch11
Pasandi GPedram M(2019)PBMap: A Path Balancing Technology Mapping Algorithm for Single Flux Quantum Logic CircuitsIEEE Transactions on Applied Superconductivity10.1109/TASC.2018.288034329:4(1-14)Online publication date: Jun-2019
https://doi.org/10.1109/TASC.2018.2880343
Macii ECalimera AMacii APoncino M(2017) Logic Synthesis of CMOS Circuits and Beyond Nanoelectronics10.1002/9783527800728.ch14(331-362)Online publication date: 7-Apr-2017
https://doi.org/10.1002/9783527800728.ch14
Monteiro JPatel RTiwari V(2016)Power Analysis and Optimization from Circuitto Register-Transfer LevelsElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-5(57-76)Online publication date: 14-Apr-2016
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Khatri SShenoy NGiomi JKhouja A(2016)Logic SynthesisElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-4(27-55)Online publication date: 14-Apr-2016
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Lanik JMaler O(2015)On Switching Aware Synthesis for Combinational CircuitsHardware and Software: Verification and Testing10.1007/978-3-319-26287-1_17(276-291)Online publication date: 28-Nov-2015
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Joshi V(2013)Probabilistic power analysis technique for low power VLSI circuits2013 IEEE 8th International Conference on Industrial and Information Systems10.1109/ICIInfS.2013.6732055(616-621)Online publication date: Dec-2013
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Li XWang LXia Y(2013)A new transition density calculation method for XOR gate2013 International Conference on Anti-Counterfeiting, Security and Identification (ASID)10.1109/ICASID.2013.6825295(1-4)Online publication date: Oct-2013
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Zhang HWang P(2012)Greedy algorithm based XNOR/OR gates decomposition2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology10.1109/ICSICT.2012.6467770(1-3)Online publication date: Oct-2012
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Zhang ZChen D(2012)Challenges and opportunities of ESL design automation2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology10.1109/ICSICT.2012.6467670(1-4)Online publication date: Oct-2012
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Low-power technology mapping for FPGA architectures with dual supply voltages

An exact gate decomposition algorithm for low-power technology mapping

Power efficient technology decomposition and mapping under an extended power consumption model

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Low-power technology mapping for FPGA architectures with dual supply voltages

An exact gate decomposition algorithm for low-power technology mapping

Power efficient technology decomposition and mapping under an extended power consumption model

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