research-article

Efficiency trends and limits from comprehensive microarchitectural adaptivity

Authors:

Benjamin C. Lee,

David BrooksAuthors Info & Claims

ASPLOS XIII: Proceedings of the 13th international conference on Architectural support for programming languages and operating systems

Pages 36 - 47

https://doi.org/10.1145/1346281.1346288

Published: 01 March 2008 Publication History

Abstract

Increasing demand for power-efficient, high-performance computing requires tuning applications and/or the underlying hardware to improve the mapping between workload heterogeneity and computational resources. To assess the potential benefits of hardware tuning, we propose a framework that leverages synergistic interactions between recent advances in (a) sampling, (b) predictive modeling, and (c) optimization heuristics. This framework enables qualitatively new capabilities in analyzing the performance and power characteristics of adaptive microarchitectures. For the first time, we are able to simultaneously consider high temporal and comprehensive spatial adaptivity. In particular, we optimize efficiency for many, short adaptive intervals and identify the best configuration of 15 parameters, which define a space of 240B point.

With frequent sub-application reconfiguration and a fully reconfigurable hardware substrate, adaptive microarchitectures achieve bips³/w efficiency gains of up to 5.3x (median 2.4x) relative to their static counterparts already optimized for a given application. This 5.3x efficiency gain is derived from a 1.6x performance gain and 0.8x power reduction. Although several applications achieve a significant fraction of their potential efficiency with as few as three adaptive parameters, the three most significant parameters differ across applications. These differences motivate a hardware substrate capable of comprehensive adaptivity to meet these diverse application requirements.

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Cited By

Saravanan VPillai ANaik K(2021)Mathematical Modelling of an Application Specific Processor Architecture with Power Optimization2021 IEEE International Women in Engineering (WIE) Conference on Electrical and Computer Engineering (WIECON-ECE)10.1109/WIECON-ECE54711.2021.9829608(55-58)Online publication date: 4-Dec-2021
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Wan CSantriaji MRogers EHoffmann HMaire MLu SGavrilovska AZadok E(2020)ALERTProceedings of the 2020 USENIX Conference on Usenix Annual Technical Conference10.5555/3489146.3489170(353-369)Online publication date: 15-Jul-2020
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Dublish SNagarajan VTopham N(2019)Poise: Balancing Thread-Level Parallelism and Memory System Performance in GPUs Using Machine Learning2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2019.00061(492-505)Online publication date: Feb-2019
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Index Terms

Efficiency trends and limits from comprehensive microarchitectural adaptivity
1. Computing methodologies
  1. Modeling and simulation
    1. Model development and analysis
2. Hardware
  1. Hardware validation

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cover image ACM Conferences

ASPLOS XIII: Proceedings of the 13th international conference on Architectural support for programming languages and operating systems

March 2008

352 pages

ISBN:9781595939586

DOI:10.1145/1346281

General Chair:
Susan Eggers
University of Washington, USA
,
Program Chair:
James Larus
Microsoft Research, USA

ACM SIGPLAN Notices Volume 43, Issue 3
ASPLOS '08
March 2008
339 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/1353536
Issue’s Table of Contents
ACM SIGARCH Computer Architecture News Volume 36, Issue 1
ASPLOS '08
March 2008
339 pages
ISSN:0163-5964
DOI:10.1145/1353534
Issue’s Table of Contents
ACM SIGOPS Operating Systems Review Volume 42, Issue 2
ASPLOS '08
March 2008
339 pages
ISSN:0163-5980
DOI:10.1145/1353535
Issue’s Table of Contents

Copyright © 2008 ACM.

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Published: 01 March 2008

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https://doi.org/10.1109/WIECON-ECE54711.2021.9829608
Wan CSantriaji MRogers EHoffmann HMaire MLu SGavrilovska AZadok E(2020)ALERTProceedings of the 2020 USENIX Conference on Usenix Annual Technical Conference10.5555/3489146.3489170(353-369)Online publication date: 15-Jul-2020
https://dl.acm.org/doi/10.5555/3489146.3489170
Dublish SNagarajan VTopham N(2019)Poise: Balancing Thread-Level Parallelism and Memory System Performance in GPUs Using Machine Learning2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2019.00061(492-505)Online publication date: Feb-2019
https://doi.org/10.1109/HPCA.2019.00061
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