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A semi-persistent clustering technique for VLSI circuit placement

Published: 03 April 2005 Publication History

Abstract

Placement is a critical component of today's physical synthesis flow with tremendous impact on the final performance of VLSI designs. However, it accounts for a significant portion of the over-all physical synthesis runtime. With complexity and netlist size of today's VLSI design growing rapidly, clustering for placement can provide an attractive solution to manage affordable placement runtime. Such clustering, however, has to be carefully devised to avoid any adverse impact on the final placement solution quality. In this paper we present a new bottom-up clustering technique, called best-choice, targeted for large-scale placement problems. Our best-choice clustering technique operates directly on a circuit hypergraph and repeatedly clusters the globally best pair of objects. Clustering score manipulation using a priority-queue data structure enables us to identify the best pair of objects whenever clustering is performed. To improve the runtime of priority-queue-based best-choice clustering, we propose a lazy-update technique for faster updates of clustering score with almost no loss of solution quality. We also discuss a number of effective methods for clustering score calculation, balancing cluster sizes, and handling of fixed blocks. The effectiveness of our best-choice clustering methodology is demonstrated by extensive comparisons against other standard clustering techniques such as Edge-Coarsening [12] and First-Choice [13]. All clustering methods are implemented within an industrial placer CPLACE [1] and tested on several industrial benchmarks in a semi-persistent clustering context.

References

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[2]
C. J. Alpert, J. H. Huang, and A. B. Kahng, "Multilevel Circuit Partitioning," in Proc. ACM/IEEE Design Automation Conference, 1997, pp. 530--533.
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C. J. Alpert and A. B. Kahng, "A General Framework for Vertex Orderings with Application to Netlist Clustering," in Proc. ACM/IEEE Design Automation Conference, 1994, pp. 63--67.
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T. Chan, J. Cong, T. Kong, and J. Shinnerl, "Multilevel Optimization for Large-Scale Circuit Placement," in Proc. IEEE International Conference on Computer-Aided Design, 2000, pp. 171--176.
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C.-C. Chang, J. Cong, D. Pan, and X. Yuan, "Physical Hierarchy Generation with Routing Congestion Control," in Proc. ACM/IEEE International Symposium on Physical Design, 2002, pp. 36--41.
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J. Cong and S. K. Lim, "Edge Separability-Based Circuit Clustering with Application to Multilevel Circuit Partitioning," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23(3), pp. 346--357, 2004.
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B. Hu and M. Marek-Sadowska, "Fine Granularity Clustering-Based Placement," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23(4), pp. 527--536, 2004.
[12]
G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar, "Multi-level Hypergraph Partitioning: Application in VLSI Domain," in Proc. ACM/IEEE Design Automation Conference, 1997, pp. 526--529.
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G. Karypis and V. Kumar, "Multilevel k-way Hypergraph Partitioning," in Proc. ACM/IEEE Design Automation Conference, 1999, pp. 343--348.
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D. M. Schuler and E. G. Ulrich, "Clustering and Linear Placement," in Proc. ACM/IEEE Design Automation Conference, 1972, pp. 50--56.
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W.-J. Sun and C. Sechen, "Efficient and Effective Placement for Very Large Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14(5), pp. 349--359, 1995.
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M. Wang, X. Yang, and M. Sarrafzadeh, "DRAGON2000: Standard-Cell Placement Tool for Large Industry Circuits," in Proc. IEEE International Conference on Computer-Aided Design, 2001, pp. 260--263.
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M. Yildiz and P. Madden, "Global Objectives for Standard-Cell Placement," in Proc. IEEE Great Lakes Symposium on VLSI, 2001, pp. 68--72.

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cover image ACM Conferences
ISPD '05: Proceedings of the 2005 international symposium on Physical design
April 2005
258 pages
ISBN:1595930213
DOI:10.1145/1055137
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 03 April 2005

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  1. VLSI placement
  2. hypergraph clustering
  3. physical design

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ISPD05: International Symposium on Physical Design 2005
April 3 - 6, 2005
California, San Francisco, USA

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Overall Acceptance Rate 62 of 172 submissions, 36%

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