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Optimizing data placement for reducing shift operations on domain wall memories

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Weiwen JiangAuthors Info & Claims

DAC '15: Proceedings of the 52nd Annual Design Automation Conference

Article No.: 139, Pages 1 - 6

https://doi.org/10.1145/2744769.2744883

Published: 07 June 2015 Publication History

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Abstract

Domain Wall Memory (DWM) using nanowire with data access port, exhibits extraordinary high density, low power leakage, and low access latency. These properties enable DWM to become an attractive candidate for replacing traditional memories. However, data accesses on DWM may require multiple shift operations before the port points to requested data, resulting in varying access latencies. Data placement, therefore, has a significant impact on the performance of data accesses on DWM. This paper studies compiler-based optimization techniques for data placement on DWM. To the authors' best knowledge, this is the first work addressing data placement problem on DWM. We present an efficient heuristic, called Grouping-Based Data Placement (GBDP), for the data placement problem of a given data access sequence on DWM. The experimental results show that GBDP has a significant performance improvement; for example, GBDP reduces 82% shift operations on an 8-port DWM compared with non-optimized approach.

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Hui PSha EZhuge QXu RWang HTakahashi A(2023)Optimizing Data Layout for Racetrack Memory in Embedded SystemsProceedings of the 28th Asia and South Pacific Design Automation Conference10.1145/3566097.3567854(110-115)Online publication date: 16-Jan-2023
https://dl.acm.org/doi/10.1145/3566097.3567854
Xu RSha EZhuge QSong YWang HShi L(2023)Optimizing Data Placement for Hybrid SRAM+Racetrack Memory SPM in Embedded SystemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.318554842:3(847-859)Online publication date: Mar-2023
https://doi.org/10.1109/TCAD.2022.3185548
Xu RSha EZhuge QShi LGu SHou YChen YZhirnov VSasan ASavidis I(2021)Relaxed PlacementProceedings of the 2021 Great Lakes Symposium on VLSI10.1145/3453688.3461513(129-134)Online publication date: 22-Jun-2021
https://dl.acm.org/doi/10.1145/3453688.3461513
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Optimizing data placement for reducing shift operations on domain wall memories
1. Hardware

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DAC '15: Proceedings of the 52nd Annual Design Automation Conference

June 2015

1204 pages

ISBN:9781450335201

DOI:10.1145/2744769

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Published: 07 June 2015

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National Natural Science Foundation of China
Chongqing High-Tech Research Program
National High Technology Research and Development Program of China (863 Program)

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DAC '15

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DAC '15: The 52nd Annual Design Automation Conference 2015

June 7 - 11, 2015

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Hui PSha EZhuge QXu RWang HTakahashi A(2023)Optimizing Data Layout for Racetrack Memory in Embedded SystemsProceedings of the 28th Asia and South Pacific Design Automation Conference10.1145/3566097.3567854(110-115)Online publication date: 16-Jan-2023
https://dl.acm.org/doi/10.1145/3566097.3567854
Xu RSha EZhuge QSong YWang HShi L(2023)Optimizing Data Placement for Hybrid SRAM+Racetrack Memory SPM in Embedded SystemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.318554842:3(847-859)Online publication date: Mar-2023
https://doi.org/10.1109/TCAD.2022.3185548
Xu RSha EZhuge QShi LGu SHou YChen YZhirnov VSasan ASavidis I(2021)Relaxed PlacementProceedings of the 2021 Great Lakes Symposium on VLSI10.1145/3453688.3461513(129-134)Online publication date: 22-Jun-2021
https://dl.acm.org/doi/10.1145/3453688.3461513
Xu RSha EZhuge QShi LGu S(2020)Architectural Exploration on Racetrack Memories2020 IEEE 33rd International System-on-Chip Conference (SOCC)10.1109/SOCC49529.2020.9524792(31-36)Online publication date: 8-Sep-2020
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Blasing RKhan AFilippou PGarg CHameed FCastrillon JParkin S(2020)Magnetic Racetrack Memory: From Physics to the Cusp of Applications Within a DecadeProceedings of the IEEE10.1109/JPROC.2020.2975719(1-19)Online publication date: 2020
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Xu RSha EZhuge QGu SShi L(2020)Optimizing Data Placement for Hybrid SPM with SRAM and Racetrack Memory2020 IEEE 38th International Conference on Computer Design (ICCD)10.1109/ICCD50377.2020.00075(409-416)Online publication date: Oct-2020
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Zhang HWei BLu YShu J(2019)SIRM: Shift Insensitive Racetrack Main MemoryNetwork and Parallel Computing10.1007/978-3-030-30709-7_33(355-360)Online publication date: 23-Aug-2019
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Zhang HZhang CHu QYang CShu JShin Y(2018)Performance analysis on structure of racetrack memoryProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201700(367-374)Online publication date: 22-Jan-2018
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Zhang HZhang CHu QYang CShu J(2018)Performance analysis on structure of racetrack memory2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2018.8297351(367-374)Online publication date: Jan-2018
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Relaxed Placement: Minimizing Shift Operations for Racetrack Memory in Hybrid SPM

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