research-article

Deflection routing in 3D network-on-chip with limited vertical bandwidth

Authors:

Kiyoung ChoiAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 18, Issue 4

Article No.: 50, Pages 1 - 22

https://doi.org/10.1145/2505011

Published: 25 October 2013 Publication History

Abstract

This article proposes a deflection routing for 3D NoC with serialized TSVs for vertical links. Compared to buffered routing, deflection routing provides area- and power-efficient communication and little loss of performance under low to medium traffic load. Under 3D environments, the deflection routing can yield even better performance than buffered routing when key aspects are properly taken into account. However, the existing deflection routing technique cannot be directly applied because the serialized TSV links will take longer time to send data than ordinary planar links and cause many problems. A naive deflection through a TSV link can cause significantly longer latency and more energy consumption even for communications through planar links. This article proposes a method to mitigate the effect and also solve arising deadlock and livelock problems. Evaluation of the proposed scheme shows its effectiveness in throughput, latency, and energy consumption.

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Cited By

Kunthara RJames RSleeba SJose J(2021)Traffic aware routing in 3D NoC using interleaved asymmetric edge routersNano Communication Networks10.1016/j.nancom.2020.10033427(100334)Online publication date: Mar-2021
https://doi.org/10.1016/j.nancom.2020.100334
Han KLee JLee JLee WPedram M(2018)TEI-NoCIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.269326937:2(458-471)Online publication date: 1-Feb-2018
https://dl.acm.org/doi/10.1109/TCAD.2017.2693269
Liu WMa SHuang LWang Z(2018)The Design of NoC-Side Memory Access Scheduling for Energy-Efficient GPGPUsInternational Journal of Parallel Programming10.1007/s10766-017-0521-246:4(722-735)Online publication date: 1-Aug-2018
https://dl.acm.org/doi/10.1007/s10766-017-0521-2
Show More Cited By

Index Terms

Deflection routing in 3D network-on-chip with limited vertical bandwidth
1. Hardware
  1. Integrated circuits
    1. Interconnect

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 18, Issue 4

Special Section on Networks on Chip: Architecture, Tools, and Methodologies

October 2013

380 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/2541012

Issue’s Table of Contents

Copyright © 2013 ACM.

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 25 October 2013

Accepted: 01 July 2013

Revised: 01 June 2013

Received: 01 January 2013

Published in TODAES Volume 18, Issue 4

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Cited By

Kunthara RJames RSleeba SJose J(2021)Traffic aware routing in 3D NoC using interleaved asymmetric edge routersNano Communication Networks10.1016/j.nancom.2020.10033427(100334)Online publication date: Mar-2021
https://doi.org/10.1016/j.nancom.2020.100334
Han KLee JLee JLee WPedram M(2018)TEI-NoCIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.269326937:2(458-471)Online publication date: 1-Feb-2018
https://dl.acm.org/doi/10.1109/TCAD.2017.2693269
Liu WMa SHuang LWang Z(2018)The Design of NoC-Side Memory Access Scheduling for Energy-Efficient GPGPUsInternational Journal of Parallel Programming10.1007/s10766-017-0521-246:4(722-735)Online publication date: 1-Aug-2018
https://dl.acm.org/doi/10.1007/s10766-017-0521-2
Runge AKolla R(2017)TwoPhasesJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2016.12.00175:C(145-154)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1016/j.sysarc.2016.12.001
Xiang DShen K(2016)A New Unicast-Based Multicast Scheme for Network-on-Chip Router and Interconnect TestingACM Transactions on Design Automation of Electronic Systems10.1145/282150621:2(1-23)Online publication date: 28-Jan-2016
https://dl.acm.org/doi/10.1145/2821506
Xiang DChakrabarty KFujiwara H(2016)Multicast-Based Testing and Thermal-Aware Test Scheduling for 3D ICs with a Stacked Network-on-ChipIEEE Transactions on Computers10.1109/TC.2015.249354865:9(2767-2779)Online publication date: 1-Sep-2016
https://dl.acm.org/doi/10.1109/TC.2015.2493548
Lee JKang KChoi K(2015)REDELFACM Journal on Emerging Technologies in Computing Systems10.1145/275156012:3(1-22)Online publication date: 21-Sep-2015
https://dl.acm.org/doi/10.1145/2751560
Chen HLi YTan SHuang XWang HWong N(2015)H-Matrix-Based Finite-Element-Based Thermal Analysis for 3D ICsACM Transactions on Design Automation of Electronic Systems10.1145/271456320:4(1-25)Online publication date: 28-Sep-2015
https://dl.acm.org/doi/10.1145/2714563

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