Pencil: a pipelined algorithm for distributed stencils
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Combining loop transformations considering caches and scheduling
MICRO 29: Proceedings of the 29th annual ACM/IEEE international symposium on MicroarchitectureThe performance of modern microprocessors is greatly affected by cache behavior, instruction scheduling, register allocation and loop overhead. High level loop transformations such as fission, fusion, tiling, interchanging and outer loop unrolling (e.g.,...
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- General Chair:
- Christine Cuicchi,
- Program Chairs:
- Irene Qualters,
- William Kramer
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- IEEE CS
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