A detailed methodology to compute soft error rates in advanced technologies
Abstract
System reliability has become a key design aspect for computer systems due to the aggressive technology miniaturization. Errors are typically dominated by transient faults due to radiation and are strongly related to the technology used to build hardware. However, there is a lack of detailed methodologies to model and fairly compare Soft Error Rates (SER) across different advanced technologies. This work first describes a common methodology that from (1) technology models, (2) location (latitude, longitude and altitude), (3) operating conditions and (4) circuit descriptions (i.e. SRAM, latches, logic gates) can obtain accurate Soft Error Rates. Then, we use it to characterize soft errors through current and future technologies. Results at the technology layer show that new technologies, such as FinFET and SOI, can reduce SER up to 100× while the location can increase SER up to 650×.
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- A detailed methodology to compute soft error rates in advanced technologies
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- IMEC: IMEC
- Systematic: Systematic Paris-Region Systems & ICT Cluster
- DREWAG: DREWAG
- AENEAS: AENEAS
- Technical University of Dresden
- CMP: Circuits Multi Projets
- PENTA: PENTA
- CISCO
- OFFIS: Oldenburger Institut für Informatik
- Goethe University: Goethe University Frankfurt
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EDA Consortium
San Jose, CA, United States
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Published: 14 March 2016
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