research-article

Variation-aware logic mapping for crossbar nano-architectures

Authors:

Mehdi B. TahooriAuthors Info & Claims

ASPDAC '11: Proceedings of the 16th Asia and South Pacific Design Automation Conference

Pages 317 - 322

Published: 25 January 2011 Publication History

Abstract

Programmable nano-architectures fabricated based on bottom-up self-assembly process are alternative for CMOS technology to overcome physical barriers as well as increased lithography-based fabrication costs in downscaling. Extreme process variation and high failure rate due to nondeter-ministic self assembly fabrication process pose serious challenges for logic implementation in this technology.

In this paper, we analyze the effect of variations on mapped designs and propose an efficient mapping method to reduce variation effects on crossbar nano-architectures. This method takes advantage of reconfigurability and abundance of resources for tolerating variation and improving reliability. The main idea is based on duplicating crossbar input lines as well as swapping rows (columns) of a crossbar to reduce the output dependency and be able to reduce delay variation. Experimental results on a set of benchmarks show that the proposed method can reduce critical path delay up to 74% (57% in average).

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Cited By

Zamani MMirzaei HTahoori M(2013)ILP formulations for variation/defect-tolerant logic mapping on crossbar nano-architecturesACM Journal on Emerging Technologies in Computing Systems10.1145/24916809:3(1-21)Online publication date: 8-Oct-2013
https://dl.acm.org/doi/10.1145/2491680
Zamani MTahoori MBrunvard EStevens KCavallaro JZhang T(2012)Reliable logic mapping on Nano-PLA architecturesProceedings of the great lakes symposium on VLSI10.1145/2206781.2206809(107-110)Online publication date: 3-May-2012
https://dl.acm.org/doi/10.1145/2206781.2206809
Zamani MTahoori M(2011)Self-timed nano-PLAProceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures10.1109/NANOARCH.2011.5941487(78-85)Online publication date: 8-Jun-2011
https://dl.acm.org/doi/10.1109/NANOARCH.2011.5941487

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Published In

cover image ACM Conferences

ASPDAC '11: Proceedings of the 16th Asia and South Pacific Design Automation Conference

January 2011

841 pages

ISBN:9781424475162

Sponsors

IEEE
IPSJ
SIGDA: ACM Special Interest Group on Design Automation
IEICE ESS: Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
IEICE

Publisher

IEEE Press

Publication History

Published: 25 January 2011

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ASPDAC '11

Sponsor:

SIGDA
IEICE ESS

ASPDAC '11: 16th Asia and South Pacific Design Automation Conference

January 25 - 28, 2011

Yokohama, Japan

Acceptance Rates

Overall Acceptance Rate 466 of 1,454 submissions, 32%

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January 20 - 23, 2025

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Cited By

Zamani MMirzaei HTahoori M(2013)ILP formulations for variation/defect-tolerant logic mapping on crossbar nano-architecturesACM Journal on Emerging Technologies in Computing Systems10.1145/24916809:3(1-21)Online publication date: 8-Oct-2013
https://dl.acm.org/doi/10.1145/2491680
Zamani MTahoori MBrunvard EStevens KCavallaro JZhang T(2012)Reliable logic mapping on Nano-PLA architecturesProceedings of the great lakes symposium on VLSI10.1145/2206781.2206809(107-110)Online publication date: 3-May-2012
https://dl.acm.org/doi/10.1145/2206781.2206809
Zamani MTahoori M(2011)Self-timed nano-PLAProceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures10.1109/NANOARCH.2011.5941487(78-85)Online publication date: 8-Jun-2011
https://dl.acm.org/doi/10.1109/NANOARCH.2011.5941487

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