research-article

Synthesizing Brain-network-inspired Interconnections for Large-scale Network-on-chips

Authors:

Feng WuAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 27, Issue 1

Article No.: 9, Pages 1 - 30

https://doi.org/10.1145/3480961

Published: 15 October 2021 Publication History

Abstract

Brain network is a large-scale complex network with scale-free, small-world, and modularity properties, which largely supports this high-efficiency massive system. In this article, we propose to synthesize brain-network-inspired interconnections for large-scale network-on-chips. First, we propose a method to generate brain-network-inspired topologies with limited scale-free and power-law small-world properties, which have a low total link length and extremely low average hop count approximately proportional to the logarithm of the network size. In addition, given the large-scale applications, considering the modularity of the brain-network-inspired topologies, we present an application mapping method, including task mapping and deterministic deadlock-free routing, to minimize the power consumption and hop count. Finally, a cycle-accurate simulator \(BookSim2\) is used to validate the architecture performance with different synthetic traffic patterns and large-scale test cases, including real-world communication networks for the graph processing application. Experiments show that, compared with other topologies and methods, the brain-network-inspired network-on-chips (NoCs) generated by the proposed method present significantly lower average hop count and lower average latency. Especially in graph processing applications with a power-law and tightly coupled inter-core communication, the brain-network-inspired NoC has up to 70% lower average hop count and 75% lower average latency than mesh-based NoCs.

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Cited By

Shahrani ARizwan AAlgarni AAlissa KShabaz MSingh BZaki J(2023)A Deep Learning Network-on-Chip (NoC)-Based Switch-Router to Enhance Information Security in Resource-Constrained DevicesJournal of Circuits, Systems and Computers10.1142/S021812662450064633:04Online publication date: 31-Aug-2023
https://doi.org/10.1142/S0218126624500646
Ge MNi XChen SKang Y(2022)Generating Brain-Network-Inspired Topologies for Large-Scale NoCs on Monolithic 3D ICsIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2021.310734069:3(1552-1556)Online publication date: Mar-2022
https://doi.org/10.1109/TCSII.2021.3107340
Berndt AMeinhardt CReis AButzen P(2022)Optimizing machine learning logic circuits with constant signal propagationIntegration, the VLSI Journal10.1016/j.vlsi.2022.08.00487:C(293-305)Online publication date: 1-Nov-2022
https://dl.acm.org/doi/10.1016/j.vlsi.2022.08.004

Index Terms

Synthesizing Brain-network-inspired Interconnections for Large-scale Network-on-chips
1. Hardware
  1. Electronic design automation
2. Networks
  1. Network types
    1. Network on chip

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cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 27, Issue 1

January 2022

230 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/3483335

Editor:
X. Sharon Hu
University of Notre Dame, USA

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Publication History

Published: 15 October 2021

Accepted: 01 July 2021

Revised: 01 May 2021

Received: 01 February 2021

Published in TODAES Volume 27, Issue 1

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National Key R&D Program of China
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Cited By

Shahrani ARizwan AAlgarni AAlissa KShabaz MSingh BZaki J(2023)A Deep Learning Network-on-Chip (NoC)-Based Switch-Router to Enhance Information Security in Resource-Constrained DevicesJournal of Circuits, Systems and Computers10.1142/S021812662450064633:04Online publication date: 31-Aug-2023
https://doi.org/10.1142/S0218126624500646
Ge MNi XChen SKang Y(2022)Generating Brain-Network-Inspired Topologies for Large-Scale NoCs on Monolithic 3D ICsIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2021.310734069:3(1552-1556)Online publication date: Mar-2022
https://doi.org/10.1109/TCSII.2021.3107340
Berndt AMeinhardt CReis AButzen P(2022)Optimizing machine learning logic circuits with constant signal propagationIntegration, the VLSI Journal10.1016/j.vlsi.2022.08.00487:C(293-305)Online publication date: 1-Nov-2022
https://dl.acm.org/doi/10.1016/j.vlsi.2022.08.004

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