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Verilog HDL and its ancestors and descendants

Authors:

Simon DavidmannAuthors Info & Claims

Proceedings of the ACM on Programming Languages, Volume 4, Issue HOPL

Article No.: 87, Pages 1 - 90

https://doi.org/10.1145/3386337

Published: 12 June 2020 Publication History

Abstract

This paper describes the history of the Verilog hardware description language (HDL), including its influential predecessors and successors. Since its creation in 1984 and first sale in 1985, Verilog has completely revolutionized the design of hardware. Verilog enabled the development and wide acceptance of logic synthesis. For large-scale digital logic design, previous schematic-based techniques have transformed into textual register-transfer level (RTL) descriptions written in Verilog. As of 2018 about 80% of integrated circuit design teams worldwide use Verilog and its compatible descendant SystemVerilog.

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Sharma ASeal DHariharan V(2024)CPU 101: Design of a Simple Microprocessor from First Principles2024 IEEE 5th India Council International Subsections Conference (INDISCON)10.1109/INDISCON62179.2024.10744370(1-6)Online publication date: 22-Aug-2024
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Index Terms

Verilog HDL and its ancestors and descendants
1. Hardware
  1. Electronic design automation

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cover image Proceedings of the ACM on Programming Languages

Proceedings of the ACM on Programming Languages Volume 4, Issue HOPL

June 2020

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EISSN:2475-1421

DOI:10.1145/3406494

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Cited By

Sharma ASeal DHariharan V(2024)CPU 101: Design of a Simple Microprocessor from First Principles2024 IEEE 5th India Council International Subsections Conference (INDISCON)10.1109/INDISCON62179.2024.10744370(1-6)Online publication date: 22-Aug-2024
https://doi.org/10.1109/INDISCON62179.2024.10744370
Zhang ZLi YXia LXue JWu JMao X(2024)An effective fault localization approach for Verilog based on enhanced contextsFrontiers of Computer Science10.1007/s11704-024-2622-618:5Online publication date: 6-Jun-2024
https://doi.org/10.1007/s11704-024-2622-6
Emami MKashani SKamahori KPourghannad MRaj RLarus JAamodt TSwift MJerger N(2023)Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous ParallelismProceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 410.1145/3623278.3624750(219-237)Online publication date: 25-Mar-2023
https://dl.acm.org/doi/10.1145/3623278.3624750
Kilincceker OTurk EBelli FChallenger M(2022)Model-based ideal testing of hardware description language (HDL) programsSoftware and Systems Modeling (SoSyM)10.1007/s10270-021-00934-621:3(1209-1240)Online publication date: 1-Jun-2022
https://dl.acm.org/doi/10.1007/s10270-021-00934-6
Lööw AHriţcu CPopescu A(2021)Lutsig: a verified Verilog compiler for verified circuit developmentProceedings of the 10th ACM SIGPLAN International Conference on Certified Programs and Proofs10.1145/3437992.3439916(46-60)Online publication date: 17-Jan-2021
https://dl.acm.org/doi/10.1145/3437992.3439916

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