survey

Probabilistic Worst-Case Timing Analysis: Taxonomy and Comprehensive Survey

Authors:

Francisco J. Cazorla,

Leonidas Kosmidis,

Enrico Mezzetti,

Carles Hernandez,

Tullio VardanegaAuthors Info & Claims

ACM Computing Surveys (CSUR), Volume 52, Issue 1

Article No.: 14, Pages 1 - 35

https://doi.org/10.1145/3301283

Published: 13 February 2019 Publication History

Abstract

The unabated increase in the complexity of the hardware and software components of modern embedded real-time systems has given momentum to a host of research in the use of probabilistic and statistical techniques for timing analysis. In the last few years, that front of investigation has yielded a body of scientific literature vast enough to warrant some comprehensive taxonomy of motivations, strategies of application, and directions of research. This survey addresses this very need, singling out the principal techniques in the state of the art of timing analysis that employ probabilistic reasoning at some level, building a taxonomy of them, discussing their relative merit and limitations, and the relations among them. In addition to offering a comprehensive foundation to savvy probabilistic timing analysis, this article also identifies the key challenges to be addressed to consolidate the scientific soundness and industrial viability of this emerging field.

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Stack distance based worst-case instruction cache performance analysis
SAC '11: Proceedings of the 2011 ACM Symposium on Applied Computing

The worst-case execution time (WCET) analysis is critical to ensure the schedulability and correctness of hard real-time systems. Modern microprocessors, however, make the WCET analysis complicated, mainly because of their performance acceleration ...

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cover image ACM Computing Surveys

ACM Computing Surveys Volume 52, Issue 1

January 2020

758 pages

ISSN:0360-0300

EISSN:1557-7341

DOI:10.1145/3309872

Editor:
Sartaj Sahni
Department of Computer and Information Science and Engineering

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Copyright © 2019 ACM.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 February 2019

Accepted: 01 October 2018

Revised: 01 August 2018

Received: 01 July 2017

Published in CSUR Volume 52, Issue 1

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Spanish Ministry of Science and Innovation
HiPEAC Network of Excellence
Spanish Ministry of Economy and Competitiveness under Juan de la Cierva-Incorporación postdoctoral fellowship
research and innovation programme
European Research Council (ERC) under the European Union’s Horizon 2020
Ministry of Economy and Competitiveness under a Ramon y Cajal postdoctoral fellowship

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