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Performance-driven scheduling with bit-level chaining

Authors:

Sanghun Park,

Kiyoung ChoiAuthors Info & Claims

DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Pages 286 - 291

https://doi.org/10.1145/309847.309932

Published: 01 June 1999 Publication History

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References

[1]

K. S. Hwang, A. E. Casavant, C. T. Chang, and M. A. d'Abreu, "Scheduling and hardware sharing in pipelined data paths," in Proc. Int'l Conf. on Computer Aided Design, 1989, pp. 24-27.

Google Scholar

[2]

N. Park and A. C. Parker, "Sehwa: A software package for synthesis of pipelines from behavioral specifications," IEEE Trans. on Computer-Aided Design, pp. 356-370, Mar. 1988.

Digital Library

Google Scholar

[3]

S. Devadas and A. R. Newton, "Data path synthesis from behavioral description: An algorithmic approach," in Proc. Int'l Symposium on Circuits and Systems, 1987, pp. 298-401.

Google Scholar

[4]

M. R. Corazao, M. A. Khalaf, L. M. Guerra M. Potkonjak, and J. Rabaey, "Performance optimization using template mapping for datapath-intensive highlevel synthesis," IEEE Trans. on Computer-Aided Design, vol. 15, no. 8, pp. 877-888, Aug. 1996.

Digital Library

Google Scholar

[5]

R Kanthamanon, G. R. Hellestrand, and R. L.K. Chart, "A context sensitive scheduling technique under resource constraints," in P1vc. Asia Pacific Conf. on Hardware Description Language, 1997, pp. 92-99.

Google Scholar

[6]

S. Narayan and D. D. Gajski, "System clock estimation based on clock slack minimization," in Proc. European Design & Test Conf., 1992, pp. 66-71.

Digital Library

Google Scholar

[7]

S. Parameswaran, R Jha, and N. Dutt, "Resynthesizing controllers for minimum execution time," in Proc. Asia Pacific Conf. on Hardware Description Language, 1994, pp. 111-117.

Google Scholar

[8]

H.R Juan, D. D. Gajski, and V. Chaiyakul, "Clock-driven performance optimization in interactive behavioral synthesis," in P~vc. Int' l Conf. on Computer Aided Design, 1996, pp. 154-157.

Digital Library

Google Scholar

[9]

S. Park and K. Choi, "Latency minimisation by system clock optimisation," lEE Elect~vnics Letters, vol. 34, no. 9, pp. 862-864, Apr. 1998.

Google Scholar

[10]

R G. Paulin and J. R Knight, "Force-directed scheduling for the behavioral synthesis of asic's," IEEE Trans. on Computer-Aided Design, vol. 8, no. 6, pp. 661-679, June 1989.

Crossref

Google Scholar

[11]

W. F. J. Verhaegh, P. E. R. Lippens, E. H. L. Aarts J.H.M. Korst, J. L. van Meerbergen, and A. van der Weft, "Improved force-directed scheduling in highthroughput digital signal processing," IEEE Trans. on Computer-Aided Design, vol. 14, no. 8, pp. 945-960, Aug. 1995.

Digital Library

Google Scholar

[12]

R. Camposano, "Path-based scheduling for synthesis," IEEE Trans. on Computer-AidedDesign, vol. 10, no. 1, pp. 85-93, Jan. 1991.

Digital Library

Google Scholar

[13]

C.T. Hwang, J.H. Lee, and Y.C. Hsu, "A formal approach to the scheduling problem in high level synthesis," IEEE Trans. on Computer-Aided Design, vol. 10, no. 4, pp. 464-475, Apr. 1991.

Digital Library

Google Scholar

[14]

J. Rabaey, C. Chu, R Hoang, and M. Potkonjak, "Fast prototyping of datapathintensive architectures," IEEE Design & Test of Computers, pp. 40-51, June 1991.

Digital Library

Google Scholar

[15]

K. Hwang, "Computer arithmetic: Principles, architecture, and design," John Wiley & Sons, 1979.

Digital Library

Google Scholar

[16]

S. Wu, "Hyper's hardware library," M.S. thesis, EECS Department, U.C. Berkeley, 1993-1995.

Google Scholar

[17]

O. Bentz, "A hardware mapper for the hyper high level synthesis system," M.S. thesis, EECS Department, U.C. Berkeley, 1993.

Google Scholar

[18]

S. Note, F. Catthoor, G. Goossens, and H. De Man, "Combined hardware selection and pipelining in high performance deat-path design," in P~vc. Int'l Conf. on Computer Design, 1990, pp. 328-331.

Google Scholar

[19]

M. Potkonjak and J. Rabaey, "Retiming for scheduling," in P1vc. IEEE Workshop on VLSI Signal P1vcessing, 1990.

Google Scholar

[20]

E.M. Sentovich and et al., "Sequential circuit design using synthesis and optimization," in P~vc. Int' l Conf. on Computer Aided Design, 1992, pp. 328-333.

Digital Library

Google Scholar

[21]

A. Aziz, F. Balarin, R. Brayton and A. Sangiovanni-Vincentelli, "Sequential synthesis using sis," in P~vc. Int'l Conf. on Computer Aided Design, 1995, pp. 612-617.

Digital Library

Google Scholar

[22]

S. Park and K. Choi, "Sequential circuit optimization by fsm transformation," in P1vc. Asia Pacific Conf. on Hardware Description Language, 1998, pp. 53-58.

Google Scholar

Cited By

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TERADA KYANAGISAWA MTOGAWA N(2015)A High-Level Synthesis Algorithm with Inter-Island Distance Based Operation Chainings for RDR ArchitecturesIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E98.A.1366E98.A:7(1366-1375)Online publication date: 2015
https://doi.org/10.1587/transfun.E98.A.1366
Mittal KJoshi AMutyam M(2011)Timing variation-aware scheduling and resource binding in high-level synthesisACM Transactions on Design Automation of Electronic Systems (TODAES)10.1145/2003695.200370016:4(1-19)Online publication date: 27-Oct-2011
https://dl.acm.org/doi/10.1145/2003695.2003700
Auge IDonnet FPetrot F(2003)Retiming finite state machines to control hardened data-paths16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings.10.1109/SBCCI.2003.1232804(41-46)Online publication date: 2003
https://doi.org/10.1109/SBCCI.2003.1232804
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Index Terms

Performance-driven scheduling with bit-level chaining
1. Applied computing
  1. Physical sciences and engineering
    1. Engineering
2. Software and its engineering
  1. Software organization and properties
    1. Contextual software domains
      1. Operating systems
        Process management

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Published In

DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation Conference

June 1999

1000 pages

ISBN:1581131097

DOI:10.1145/309847

Editor:
Mary Jane Irwin

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 01 June 1999

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DAC99: The 36th ACM/IEEE-CAS/EDAC Design Automation Conference

June 21 - 25, 1999

Louisiana, New Orleans, USA

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DAC '99 Paper Acceptance Rate 154 of 451 submissions, 34%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

TERADA KYANAGISAWA MTOGAWA N(2015)A High-Level Synthesis Algorithm with Inter-Island Distance Based Operation Chainings for RDR ArchitecturesIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E98.A.1366E98.A:7(1366-1375)Online publication date: 2015
https://doi.org/10.1587/transfun.E98.A.1366
Mittal KJoshi AMutyam M(2011)Timing variation-aware scheduling and resource binding in high-level synthesisACM Transactions on Design Automation of Electronic Systems (TODAES)10.1145/2003695.200370016:4(1-19)Online publication date: 27-Oct-2011
https://dl.acm.org/doi/10.1145/2003695.2003700
Auge IDonnet FPetrot F(2003)Retiming finite state machines to control hardened data-paths16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings.10.1109/SBCCI.2003.1232804(41-46)Online publication date: 2003
https://doi.org/10.1109/SBCCI.2003.1232804
Jeon JKim DShin DChoi KGoto S(2001)High-level synthesis under multi-cycle interconnect delayProceedings of the 2001 Asia and South Pacific Design Automation Conference10.1145/370155.370576Online publication date: 30-Jan-2001
https://dl.acm.org/doi/10.1145/370155.370576
Jinhwan Jeon Daehong Kim Dongwan Shin Kiyoung Choi (2001)High-level synthesis under multi-cycle interconnect delayProceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)10.1109/ASPDAC.2001.913385(662-667)Online publication date: 2001
https://doi.org/10.1109/ASPDAC.2001.913385
Sanghun Park Kihyun Kim Hyunseok Chang Jiahwan Jeon Kiyoung Choi (1999)Backward-annotation of post-layout delay information into high-level synthesis process for performance optimizationICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)10.1109/ICVC.1999.820808(25-28)Online publication date: 1999
https://doi.org/10.1109/ICVC.1999.820808

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