research-article

Small-World Network Enabled Energy Efficient and Robust 3D NoC Architectures

Authors:

Partha Pratim PandeAuthors Info & Claims

GLSVLSI '15: Proceedings of the 25th edition on Great Lakes Symposium on VLSI

Pages 133 - 138

https://doi.org/10.1145/2742060.2742085

Published: 20 May 2015 Publication History

Abstract

Three dimensional (3D) Network-on-Chip (NoC) architectures enable design of low power and high performance communication fabrics for multicore chips. In spite of achievable performance benefits, 3D NoCs are still bottlenecked by the planar interconnects. To exploit the benefits introduced by the vertical dimension, it is imperative to explore novel 3D NoC architectures. In this paper, we propose design of a small-world (SW) network based 3D NoCs. We demonstrate that the proposed 3D SW NoC outperforms its conventional 3D mesh-based counterparts. On average, it provides ~25% reduction in the energy delay product (EDP) compared to 3D MESH without introducing any additional link overhead in presence of conventional SPLASH-2 and PARSEC benchmarks. The proposed 3D SW NoC is more robust in presence of TSV failures and performs better than fault-free 3D MESH even in the presence of 25% TSVs failure.

References

[1]

U. Y. Ogras, R. Marculescu, ""It"s a Small World After All": NoC Performance Optimization via Long-Range Link Insertion", IEEE Trans. on VLSI Systems, Vol. 14, pp. 693--706, 2006.

Digital Library

[2]

C. Teuscher, "Nature-inspired interconnects for self-assembled large-scale network-on-chip designs", e-print arXiv: arXiv:0704.2852.

[3]

V. F. Pavlidis, E. G. FriedMan, "3-D Topologies for Networks on-Chip," IEEE Trans on VLSI Systems, Vol 15, pp. 1081--1090, 2007.

Digital Library

[4]

B. S. Feero, P. P. Pande "Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation", IEEE Trans. on Computers, Vol 53, pp. 32--45, Aug. 2008.

Digital Library

[5]

A.W. Topol, et al. "Three-Dimensional Integrated Circuits," IBM Journal of Research and Development, Vol. 50, nos. 4/5, July 2006.

Digital Library

[6]

F. Li, C. Nicopoulos, T. Richardson, Y. Xie, V. Narayanan, M. Kandemir "High-Performance and Fault-Tolerant 3D NoC-Bus Hybrid Architecture Using ARB-NET Based Adaptive Monitoring Platform" IEEE Trans on Computers, Vol. 63, pp. 32--45, Aug. 2008.

Digital Library

[7]

J. Kim et al., "A novel dimensionally-decomposed router for on-chip communication in 3D architectures," in Proc. of Annual Intl. Symp. on Computer Architecture, June 2007, pp. 138--149.

Digital Library

[8]

A. M. Rahmani et al., "High-Performance and Fault-Tolerant 3D NoC-Bus Hybrid Architecture Using ARB-NET Based Adaptive Monitoring Platform", IEEE Trans. on Computers, vol 63, pp. 734--747, Mar 2014.

Digital Library

[9]

D. Vantrease et al., "Corona: System Implications of Emerging Nanophotonic Technology," In Proc. of 35th Int"l Symposium Computer Architecture, pp. 153--164, June 2008.

Digital Library

[10]

R. W. Morris, A. K. Kodi, A. Louri, R. D. Whaley "Three-Dimensional Stacked Nanophotonic Network-on-Chip Architecture with Minimal Reconfiguration", IEEE Transaction on Computers, Vol. 63, pp. 243--255, Jan. 2014.

Digital Library

[11]

T. Petermann, P. D. L. Rios, "Spatial small-world networks: a wiring-cost perspective", e-print arXiv:cond-mat/0501420.

[12]

T. Petermann, P. D. L. Rios, "Physical realizability of small-world networks", Phys. Rev. E 73, Feb 2006.

[13]

R. Kim, G. Liu, P. Wettin, R. Marculescu, D. Marculescu, P. P. Pande, "Energy-Efficient VFI-Partitioned Multicore Design Using Wireless NoC Architectures", In Proc. of Intl Conf on, CASES 2014.

Digital Library

[14]

P. Wettin et al., "Performance evaluation of wireless NoCs in presence of irregular network routing strategies," in Proc. of DATE, pp. 1--6, 2014.

Digital Library

[15]

H. Matsutani et al., "Low-Latency Wireless 3D NoCs via Randomized Shortcut Chips", in Proc. of DATE, 2014.

Digital Library

[16]

O. Lysne, T. Skeie, S. A. Reinemo, I. Theiss, "Layered Routing in Irregular Networks", IEEE Transaction on Parallel and Distributed System, vol. 17, 2006, pp. 51--65.

Digital Library

[17]

F. Dubois, A. Sheibanyrad, F. Petrot, M. Bahmani, "Elevator-First: A Deadlock-Free Distributed Routing Algorithm for Vertically Partially Connected 3D-NoCs", IEEE Trans. on Computers, vol. 62, 2013, pp. 609--615.

Digital Library

[18]

S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, A. Gupta,"The SPLASH-2 programs: characterization and methodological considerations," In Proc. of International Symposium on Computer Architecture, 1995, pp. 24--36.

Digital Library

[19]

C. Bienia, "Benchmarking modern multiprocessors," Ph.D. Dissertation, Princeton Univ., Princeton NJ, Jan. 2011.

Digital Library

[20]

I. Loi, F. Angiolini, S. Mitra, L. Benini, "Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip", IEEE Trans. Computer Aided Design of Integrated Circuit and System, vol. 30, 2011, pp. 124--134.

Digital Library

Cited By

Qiu YXiao CPeng LWang JKang ZLi SWang L(2021)A Novel Ring-based Small-World NoC for Neuromorphic Processor2021 IEEE 32nd International Conference on Application-specific Systems, Architectures and Processors (ASAP)10.1109/ASAP52443.2021.00042(234-241)Online publication date: Jul-2021
https://doi.org/10.1109/ASAP52443.2021.00042
Gupta NVaisla KKumar R(2021)Design of a Structured Hypercube Network Chip Topology Model for Energy Efficiency in Wireless Sensor Network Using Machine LearningSN Computer Science10.1007/s42979-021-00766-72:5Online publication date: 10-Jul-2021
https://doi.org/10.1007/s42979-021-00766-7
Musavvir SChatterjee AKim RHyun Kim DDoppa JPratim Pande P(2020)Power, Performance, and Thermal Trade-offs in M3D-enabled Manycore Chips2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE48585.2020.9116345(1752-1757)Online publication date: Mar-2020
https://doi.org/10.23919/DATE48585.2020.9116345
Show More Cited By

Index Terms

Small-World Network Enabled Energy Efficient and Robust 3D NoC Architectures
1. Networks
  1. Network properties
    1. Network structure

Recommendations

Design Space Exploration of 3D Network-on-Chip: A Sensitivity-based Optimization Approach

High-performance and energy-efficient Network-on-Chip (NoC) architecture is one of the crucial components of the manycore processing platforms. A very promising NoC architecture recently proposed in the literature is the three-dimensional small-world ...
Optimizing 3D NoC Design for Energy Efficiency: A Machine Learning Approach
ICCAD '15: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design

Three-dimensional (3D) Network-on-Chip (NoC) is an emerging technology that has the potential to achieve high performance with low power consumption for multicore chips. However, to fully realize their potential, we need to consider novel 3D NoC ...
Analyzing power-thermal-performance trade-offs in a high-performance 3D NoC architecture
Abstract
The emergence of three-dimensional (3D) network-on-chip (NoC) has revolutionized the design of high-performance and energy efficient manycore chips. However, in general, 3D NoC architectures still suffer from high power density and the ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

GLSVLSI '15: Proceedings of the 25th edition on Great Lakes Symposium on VLSI

May 2015

418 pages

ISBN:9781450334747

DOI:10.1145/2742060

General Chairs:
Alex K. Jones
University of Pittsburgh, USA
,
Hai (Helen) Li
University of Pittsburgh, USA
,
Program Chairs:
Ayse K. Coskun
Boston University, USA
,
Martin Margala
University of Massachusetts, Lowell, USA

Copyright © 2015 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

In-Cooperation

IEEE CEDA
IEEE CASS

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 20 May 2015

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Funding Sources

US National Science Foundation
Army Research Office

Conference

GLSVLSI '15

Sponsor:

SIGDA

GLSVLSI '15: Great Lakes Symposium on VLSI 2015

May 20 - 22, 2015

Pennsylvania, Pittsburgh, USA

Acceptance Rates

GLSVLSI '15 Paper Acceptance Rate 41 of 148 submissions, 28%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

Upcoming Conference

GLSVLSI '25

Sponsor:
sigda

Great Lakes Symposium on VLSI 2025

June 30 - July 2, 2025

New Orleans , LA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

13
Total Citations
View Citations
233
Total Downloads

Downloads (Last 12 months)15
Downloads (Last 6 weeks)0

Reflects downloads up to 18 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

Qiu YXiao CPeng LWang JKang ZLi SWang L(2021)A Novel Ring-based Small-World NoC for Neuromorphic Processor2021 IEEE 32nd International Conference on Application-specific Systems, Architectures and Processors (ASAP)10.1109/ASAP52443.2021.00042(234-241)Online publication date: Jul-2021
https://doi.org/10.1109/ASAP52443.2021.00042
Gupta NVaisla KKumar R(2021)Design of a Structured Hypercube Network Chip Topology Model for Energy Efficiency in Wireless Sensor Network Using Machine LearningSN Computer Science10.1007/s42979-021-00766-72:5Online publication date: 10-Jul-2021
https://doi.org/10.1007/s42979-021-00766-7
Musavvir SChatterjee AKim RHyun Kim DDoppa JPratim Pande P(2020)Power, Performance, and Thermal Trade-offs in M3D-enabled Manycore Chips2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE48585.2020.9116345(1752-1757)Online publication date: Mar-2020
https://doi.org/10.23919/DATE48585.2020.9116345
Mori H(2020)Fault Tolerance Evaluation of Small World Networks for VLSI Implementation2020 Eighth International Symposium on Computing and Networking Workshops (CANDARW)10.1109/CANDARW51189.2020.00062(286-289)Online publication date: Nov-2020
https://doi.org/10.1109/CANDARW51189.2020.00062
Moudi MOthman M(2020)On the relation between network throughput and delay curvesAutomatika10.1080/00051144.2020.177473161:3(415-424)Online publication date: 4-Jun-2020
https://doi.org/10.1080/00051144.2020.1774731
Lee DDas SDoppa JPande PChakrabarty K(2019)Impact of Electrostatic Coupling on Monolithic 3D-enabled Network on ChipACM Transactions on Design Automation of Electronic Systems10.1145/335715824:6(1-22)Online publication date: 17-Sep-2019
https://dl.acm.org/doi/10.1145/3357158
Lee DDas SDoppa JPande PChakrabarty K(2018)Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-ChipACM Transactions on Design Automation of Electronic Systems10.1145/322304623:5(1-25)Online publication date: 22-Aug-2018
https://dl.acm.org/doi/10.1145/3223046
Mori H(2018)Fault Tolerance of Small World Network Architecture2018 Sixth International Symposium on Computing and Networking Workshops (CANDARW)10.1109/CANDARW.2018.00070(344-349)Online publication date: Nov-2018
https://doi.org/10.1109/CANDARW.2018.00070
Wang KDong SJiao F(2017)TSF3D: MSV-Driven Power Optimization for Application-Specific 3D Network-on-ChipIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.265098936:7(1089-1102)Online publication date: Jul-2017
https://doi.org/10.1109/TCAD.2017.2650989
Das SDoppa JPande PChakrabarty K(2017)Design-Space Exploration and Optimization of an Energy-Efficient and Reliable 3-D Small-World Network-on-ChipIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.260428836:5(719-732)Online publication date: 1-May-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2604288
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents