research-article

Limit study of energy & delay benefits of component-specific routing

Authors:

Andre DeHonAuthors Info & Claims

FPGA '12: Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays

Pages 97 - 106

https://doi.org/10.1145/2145694.2145710

Published: 22 February 2012 Publication History

Abstract

As feature sizes scale toward atomic limits, parameter variation continues to increase, leading to increased margins in both delay and energy. The possibility of very slow devices on critical paths forces designers to increase transistor sizes, reduce clock speed and operate at higher voltages than desired in order to meet timing. With post-fabrication configurability, FPGAs have the opportunity to use slow devices on non-critical paths while selecting fast devices for critical paths. To understand the potential benefit we might gain from component-specific mapping, we quantify the margins associated with parameter variation in FPGAs over a wide range of predictive technologies (45nm-12nm) and gate sizes and show how these margins can be significantly reduced by delay-aware, component-specific routing. For the Toronto 20 benchmark set, we show that component-specific routing can eliminate delay margins induced by variation and reduce energy for energy minimal designs by 1.42-1.98×. We further show that these benefits increase as technology scales.

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Cited By

Ahmed IZhao SMeijers JTrescases OBetz V(2019)FRoC 2.0ACM Transactions on Reconfigurable Technology and Systems10.1145/335418812:4(1-28)Online publication date: 9-Sep-2019
https://dl.acm.org/doi/10.1145/3354188
Giesen HGojman BRubin RKim JDehon A(2018)Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP)ACM Transactions on Reconfigurable Technology and Systems10.1145/315822911:1(1-23)Online publication date: 26-Jan-2018
https://dl.acm.org/doi/10.1145/3158229
Ahmed IZhao SMeijers JTrescases OBetz V(2018)Automatic BRAM Testing for Robust Dynamic Voltage Scaling for FPGAs2018 28th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2018.00020(68-687)Online publication date: Aug-2018
https://doi.org/10.1109/FPL.2018.00020
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Index Terms

Limit study of energy & delay benefits of component-specific routing
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing

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Published In

cover image ACM Conferences

FPGA '12: Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays

February 2012

352 pages

ISBN:9781450311557

DOI:10.1145/2145694

General Chair:
Katherine Compton
University of Wisconsin-Madison
,
Program Chair:
Brad Hutchings
Brigham Young University

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 22 February 2012

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FPGA '12

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SIGDA

FPGA '12: ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 22 - 24, 2012

California, Monterey, USA

Acceptance Rates

FPGA '12 Paper Acceptance Rate 20 of 87 submissions, 23%;

Overall Acceptance Rate 125 of 627 submissions, 20%

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FPGA '25

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The 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 27 - March 1, 2025

Monterey , CA , USA

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Cited By

Ahmed IZhao SMeijers JTrescases OBetz V(2019)FRoC 2.0ACM Transactions on Reconfigurable Technology and Systems10.1145/335418812:4(1-28)Online publication date: 9-Sep-2019
https://dl.acm.org/doi/10.1145/3354188
Giesen HGojman BRubin RKim JDehon A(2018)Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP)ACM Transactions on Reconfigurable Technology and Systems10.1145/315822911:1(1-23)Online publication date: 26-Jan-2018
https://dl.acm.org/doi/10.1145/3158229
Ahmed IZhao SMeijers JTrescases OBetz V(2018)Automatic BRAM Testing for Robust Dynamic Voltage Scaling for FPGAs2018 28th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2018.00020(68-687)Online publication date: Aug-2018
https://doi.org/10.1109/FPL.2018.00020
Giesen HRubin RGojman BDeHon AGreene JAnderson J(2017)Quality-Time Tradeoffs in Component-Specific MappingProceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3020078.3026124(85-94)Online publication date: 22-Feb-2017
https://dl.acm.org/doi/10.1145/3020078.3026124
Linscott TGojman BRubin RDeHon AChen DGreene J(2016)Pitfalls and Tradeoffs in Simultaneous, On-Chip FPGA Delay MeasurementProceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2847263.2847334(100-104)Online publication date: 21-Feb-2016
https://dl.acm.org/doi/10.1145/2847263.2847334
Rao MOraon N(2016)Analysis of Switching Energy and Delay for Magnetic Logic Devices2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2016.17(473-478)Online publication date: Jul-2016
https://doi.org/10.1109/ISVLSI.2016.17
Giesen HGojman BRubin RKim JDeHon A(2016)Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP)2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM.2016.36(111-118)Online publication date: May-2016
https://doi.org/10.1109/FCCM.2016.36
DeHon A(2015)Fundamental Underpinnings of Reconfigurable Computing ArchitecturesProceedings of the IEEE10.1109/JPROC.2014.2387696103:3(355-378)Online publication date: Mar-2015
https://doi.org/10.1109/JPROC.2014.2387696
Tessier RPocek KDeHon A(2015)Reconfigurable Computing ArchitecturesProceedings of the IEEE10.1109/JPROC.2014.2386883103:3(332-354)Online publication date: Mar-2015
https://doi.org/10.1109/JPROC.2014.2386883
Gojman BNalmela SMehta NHowarth NDehon A(2014)GROK-LABACM Transactions on Reconfigurable Technology and Systems10.1145/25978897:4(1-23)Online publication date: 29-Dec-2014
https://dl.acm.org/doi/10.1145/2597889
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